Yaw S. Obeng

Person

Frisco, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method to attain low defectivity fully silicided gates
- Patent number 8,273,645
- Issue date Sep 25, 2012
- Texas Instruments Incorporated
- Mark Robert Visokay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,943,499
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,312
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,313
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for cleaning post-etch noble metal residues
- Patent number 7,723,199
- Issue date May 25, 2010
- Texas Instruments Incorporated
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reliably removing excess metal during metal silicide for...
- Patent number 7,700,481
- Issue date Apr 20, 2010
- Texas Instruments Incorporated
- Yaw S. Obeng
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of manufacturing metal silicide contacts
- Patent number 7,670,952
- Issue date Mar 2, 2010
- Texas Instruments Incorporated
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD TO ATTAIN LOW DEFECTIVITY FULLY SILICIDED GATES
- Publication number 20110097884
- Publication date Apr 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Mark Robert VISOKAY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI Integration Method Using SOG as a Sacrificial Planarization Layer
- Publication number 20100041231
- Publication date Feb 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT...
- Publication number 20090020791
- Publication date Jan 22, 2009
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR RELIABLY REMOVING EXCESS METAL DURING METAL SILICIDE FOR...
- Publication number 20080315322
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHOD OF MANUFACTURING METAL SILICIDE CONTACTS
- Publication number 20080230846
- Publication date Sep 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REWORK METHODOLOGY THAT PRESERVES GATE PERFORMANCE
- Publication number 20080076076
- Publication date Mar 27, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Yaw Samuel Obeng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES
- Publication number 20070298521
- Publication date Dec 27, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI integration method using SOG as a sacrificial planarization layer
- Publication number 20070173047
- Publication date Jul 26, 2007
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process For Selectively Removing Dielectric Material in the Presenc...
- Publication number 20070161246
- Publication date Jul 12, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS

Yaw S. Obeng

Person

Patents Grantslast 30 patents

Method to attain low defectivity fully silicided gates

FUSI integration method using SOG as a sacrificial planarization layer

FUSI integration method using SOG as a sacrificial planarization layer

FUSI integration method using SOG as a sacrificial planarization layer

Method for cleaning post-etch noble metal residues

Method for reliably removing excess metal during metal silicide for...

Method of manufacturing metal silicide contacts

Patents Applicationslast 30 patents

METHOD TO ATTAIN LOW DEFECTIVITY FULLY SILICIDED GATES

FUSI Integration Method Using SOG as a Sacrificial Planarization Layer

PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT...

METHOD FOR RELIABLY REMOVING EXCESS METAL DURING METAL SILICIDE FOR...

METHOD OF MANUFACTURING METAL SILICIDE CONTACTS

REWORK METHODOLOGY THAT PRESERVES GATE PERFORMANCE

METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES

FUSI integration method using SOG as a sacrificial planarization layer

Process For Selectively Removing Dielectric Material in the Presenc...