Yea Z. Kuo

Person

Fort Worth, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for a finite impulse response filter
- Patent number 8,645,442
- Issue date Feb 4, 2014
- L-3 Communications Integrated Systems, L.P.
- Yea Zong Kuo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Datapipe synchronization device
- Patent number 8,065,356
- Issue date Nov 22, 2011
- L3 Communications Integrated Systems, L.P.
- Jerry William Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable communications infrastructure for ASIC networks
- Patent number 7,921,323
- Issue date Apr 5, 2011
- L-3 Communications Integrated Systems, L.P.
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reading and writing a memory element within a programmable processi...
- Patent number 7,865,695
- Issue date Jan 4, 2011
- L3 Communications Integrated Systems, L.P.
- Jerry William Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear combiner weight memory
- Patent number 7,849,283
- Issue date Dec 7, 2010
- L-3 Communications Integrated Systems L.P.
- Jerry William Yancey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for relaying data packets
- Patent number 7,808,995
- Issue date Oct 5, 2010
- L-3 Communications Integrated Systems L.P.
- Yea Zong Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Datapipe CPU register array
- Patent number 7,734,846
- Issue date Jun 8, 2010
- L3 Communications Integrated Systems, L.P.
- Jerry William Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for data transfer
- Patent number 7,689,757
- Issue date Mar 30, 2010
- L-3 Communications Intergrated Systems, L.P.
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Datapipe CPU register array and methods of use
- Patent number 7,685,332
- Issue date Mar 23, 2010
- L3 Communications Integrated Systems, L.P.
- Jerry William Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Datapipe interpolation device
- Patent number 7,673,274
- Issue date Mar 2, 2010
- L3 Communications Integrated Systems, L.P.
- Jerry William Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for modeling concurrent behavior
- Patent number 7,603,656
- Issue date Oct 13, 2009
- L-3 Communications Integrated Systems L.P.
- Yea Zong Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for weighted overlap and add processing
- Patent number 7,587,441
- Issue date Sep 8, 2009
- L-3 Communications Integrated Systems L.P.
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for interconnection of multiple FPGA devices
- Patent number 7,444,454
- Issue date Oct 28, 2008
- L-3 Communications Integrated Systems L.P.
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for writing data with a FIFO interface
- Patent number 7,426,599
- Issue date Sep 16, 2008
- L-3 Communications Integrated Systems L.P.
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR A FINITE IMPULSE RESPONSE FILTER
- Publication number 20110153705
- Publication date Jun 23, 2011
- L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
- Yea Zong Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS
- Publication number 20080263322
- Publication date Oct 23, 2008
- L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPIPE INTERPOLATION DEVICE
- Publication number 20080263499
- Publication date Oct 23, 2008
- L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINEAR COMBINER WEIGHT MEMORY
- Publication number 20080263303
- Publication date Oct 23, 2008
- L-3 COMMUNICATIONS INTEGRATED SYSTEMS L.P.
- JERRY WILLIAM YANCEY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATAPIPE DESTINATION AND SOURCE DEVICES
- Publication number 20080263317
- Publication date Oct 23, 2008
- L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPIPE SYNCHRONIZATION DEVICE
- Publication number 20080154996
- Publication date Jun 26, 2008
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPIPE CPU REGISTER ARRAY
- Publication number 20080155138
- Publication date Jun 26, 2008
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPIPE CPU REGISTER ARRAY AND METHODS OF USE
- Publication number 20080155164
- Publication date Jun 26, 2008
- JERRY WILLIAM YANCEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for configuring FPGAs from VHDL code with reduced...
- Publication number 20080148214
- Publication date Jun 19, 2008
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and systems for relaying data packets
- Publication number 20080117908
- Publication date May 22, 2008
- Yea Zong Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems and methods for data transfer
- Publication number 20070276959
- Publication date Nov 29, 2007
- L-3 Integrated Systems Company
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for the development and distribution of a VHDL in...
- Publication number 20070106960
- Publication date May 10, 2007
- L-3 Integrated Systems Company
- Yea Zong Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable communications infrastructure for ASIC networks
- Publication number 20070101242
- Publication date May 3, 2007
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for writing data with a FIFO interface
- Publication number 20070074140
- Publication date Mar 29, 2007
- L-3 Integrated Systems Company
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for weighted overlap and add processing
- Publication number 20070005830
- Publication date Jan 4, 2007
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and systems for modeling concurrent behavior
- Publication number 20060161882
- Publication date Jul 20, 2006
- Yea Zong Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for interconnection of multiple FPGA devices
- Publication number 20050256969
- Publication date Nov 17, 2005
- Jerry W. Yancey
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method and apparatus for a finite impulse response filter

Datapipe synchronization device

Reconfigurable communications infrastructure for ASIC networks

Reading and writing a memory element within a programmable processi...

Linear combiner weight memory

Methods and systems for relaying data packets

Datapipe CPU register array

Systems and methods for data transfer

Datapipe CPU register array and methods of use

Datapipe interpolation device

Methods and systems for modeling concurrent behavior

Systems and methods for weighted overlap and add processing

Systems and methods for interconnection of multiple FPGA devices

Systems and methods for writing data with a FIFO interface

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR A FINITE IMPULSE RESPONSE FILTER

MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS

DATAPIPE INTERPOLATION DEVICE

LINEAR COMBINER WEIGHT MEMORY

DATAPIPE DESTINATION AND SOURCE DEVICES

DATAPIPE SYNCHRONIZATION DEVICE

DATAPIPE CPU REGISTER ARRAY

DATAPIPE CPU REGISTER ARRAY AND METHODS OF USE

Method and system for configuring FPGAs from VHDL code with reduced...

Methods and systems for relaying data packets

Systems and methods for data transfer

System and method for the development and distribution of a VHDL in...

Reconfigurable communications infrastructure for ASIC networks

Systems and methods for writing data with a FIFO interface

Systems and methods for weighted overlap and add processing

Methods and systems for modeling concurrent behavior

Systems and methods for interconnection of multiple FPGA devices