Yervant Zorian

Person

Santa Clara County, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded memory transparent in-system built-in self-test
- Patent number 12,002,530
- Issue date Jun 4, 2024
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip memory diagnostics
- Patent number 11,527,298
- Issue date Dec 13, 2022
- Synopsys, Inc.
- Karen Darbinyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection of address errors in memory devices using multi-segment e...
- Patent number 11,023,310
- Issue date Jun 1, 2021
- Synopsys, Inc.
- Hayk Grigoryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for SOC with optimal RSMA
- Patent number 10,789,398
- Issue date Sep 29, 2020
- Synopsys, Inc.
- Suren Martirosyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET-based memory testing using multiple read operations
- Patent number 10,192,635
- Issue date Jan 29, 2019
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Grant
FinFET-based memory testing using multiple read operations
- Patent number 10,115,477
- Issue date Oct 30, 2018
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing electronic memories based on fault and test algorithm perio...
- Patent number 9,831,000
- Issue date Nov 28, 2017
- Synopsys, Inc.
- Aram Hakhumyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Periodic signal measurement using statistical sampling
- Patent number 9,541,591
- Issue date Jan 10, 2017
- Synopsys, Inc.
- Karen Darbinyan
- G01 - MEASURING TESTING
Information Patent Grant
Generation of memory structural model based on memory layout
- Patent number 9,514,258
- Issue date Dec 6, 2016
- Synopsys, Inc.
- Karen Amirkhanyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory hard macro partition optimization for testing embedded memories
- Patent number 9,336,342
- Issue date May 10, 2016
- Synopsys, Inc.
- Yervant Zorian
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining a desirable number of segments for a multi-segment sing...
- Patent number 9,053,050
- Issue date Jun 9, 2015
- Synopsys, Inc.
- Hayk Grigoryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting random telegraph noise induced failures in an electronic...
- Patent number 8,850,277
- Issue date Sep 30, 2014
- Synopsys, Inc.
- Karen Amirkhanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Various methods and apparatuses for effective yield enhancement of...
- Patent number 8,359,553
- Issue date Jan 22, 2013
- Synopsys, Inc.
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, system and method for compressing repair data in an i...
- Patent number 8,295,108
- Issue date Oct 23, 2012
- Synopsys, Inc.
- Karen Darbinyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for external voltage test methodology of in...
- Patent number 8,225,156
- Issue date Jul 17, 2012
- Synopsys, Inc.
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Grant
Various methods and apparatuses for memory modeling using a structu...
- Patent number 8,112,730
- Issue date Feb 7, 2012
- Synopsys, Inc.
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, system and method for compressing repair data in an i...
- Patent number 7,898,882
- Issue date Mar 1, 2011
- Synopsys, Inc.
- Karen Darbinyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Various methods and apparatuses for effective yield enhancement of...
- Patent number 7,890,900
- Issue date Feb 15, 2011
- Synopsys, Inc.
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for external test methodology and initializ...
- Patent number 7,856,581
- Issue date Dec 21, 2010
- Synopsys, Inc.
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatuses for external voltage test of input-output c...
- Patent number 7,853,847
- Issue date Dec 14, 2010
- Synopsys, Inc.
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Grant
System and method for repairing a memory
- Patent number 7,788,551
- Issue date Aug 31, 2010
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory modeling using an intermediate level structural description
- Patent number 7,768,840
- Issue date Aug 3, 2010
- Virage Logic Corporation
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for verifying IP integrity in system-on-chip (SOC...
- Patent number 7,673,264
- Issue date Mar 2, 2010
- Virage Logic Corp.
- Karen Darbinyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for external delay test of input-output cir...
- Patent number 7,590,902
- Issue date Sep 15, 2009
- Virage Logic Corporation
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Grant
Input-output device testing
- Patent number 7,519,888
- Issue date Apr 14, 2009
- Virage Logic Corporation
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatuses that reduce the size of a repair data conta...
- Patent number 7,415,640
- Issue date Aug 19, 2008
- Virage Logic Corporation
- Yervant Zorian
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for repairing a memory
- Patent number 7,415,641
- Issue date Aug 19, 2008
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a command based bist for testing memories
- Patent number 7,290,186
- Issue date Oct 30, 2007
- Virage Logic Corporation
- Yervant Zorian
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method to generate a repair signature
- Patent number 7,237,154
- Issue date Jun 26, 2007
- Virage Logic Corporation
- Yervant Zorian
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, method, and system to allocate redundant components with...
- Patent number 7,149,921
- Issue date Dec 12, 2006
- Virage Logic Corporation
- Yervant Zorian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BUILT-IN SELF-TEST CIRCUIT FOR ROW HAMMERING IN MEMORY
- Publication number 20240096435
- Publication date Mar 21, 2024
- Synopsys, Inc.
- Grigor TSHAGHARYAN
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED MEMORY TRANSPARENT IN-SYSTEM BUILT-IN SELF-TEST
- Publication number 20230140090
- Publication date May 4, 2023
- Synopsys, Inc.
- Grigor TSHAGHARYAN
- G11 - INFORMATION STORAGE
Information Patent Application
FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS
- Publication number 20190035484
- Publication date Jan 31, 2019
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for SOC with Optimal RSMA
- Publication number 20180129769
- Publication date May 10, 2018
- Synopsys, Inc.
- Suren Martirosyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FinFET-Based Memory Testing Using Multiple Read Operations
- Publication number 20180130546
- Publication date May 10, 2018
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Application
Periodic Signal Measurement Using Statistical Sampling
- Publication number 20160041212
- Publication date Feb 11, 2016
- Synopsys, Inc.
- Karen Darbinyan
- G01 - MEASURING TESTING
Information Patent Application
TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIO...
- Publication number 20140380107
- Publication date Dec 25, 2014
- Aram Hakhumyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of Memory Structural Model Based on Memory Layout
- Publication number 20130346056
- Publication date Dec 26, 2013
- Synopsys, Inc.
- Karen Amirkhanyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining A Desirable Number Of Segments For A Multi-Segment Sing...
- Publication number 20130145119
- Publication date Jun 6, 2013
- Synopsys, Inc.
- Hayk Grigoryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES
- Publication number 20130080847
- Publication date Mar 28, 2013
- Synopsys, Inc.
- Yervant Zorian
- G01 - MEASURING TESTING
Information Patent Application
DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC...
- Publication number 20130019132
- Publication date Jan 17, 2013
- Synopsys Inc.
- Karen AMIRKHANYAN
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIO...
- Publication number 20130019130
- Publication date Jan 17, 2013
- Synopsys Inc.
- Aram HAKHUMYAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture, System And Method For Compressing Repair Data In An I...
- Publication number 20110119531
- Publication date May 19, 2011
- Synopsys, Inc.
- Karen Darbinyan
- G11 - INFORMATION STORAGE
Information Patent Application
VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF...
- Publication number 20100050135
- Publication date Feb 25, 2010
- Virage Logic Corporation
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Application
VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTU...
- Publication number 20090106716
- Publication date Apr 23, 2009
- Virage Logic Corporation
- Karen Aleksanyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Repairing a Memory
- Publication number 20080301507
- Publication date Dec 4, 2008
- VIRAGE LOGIC CORP.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Application
Architecture, System and Method for Compressing Repair Data in an I...
- Publication number 20080008015
- Publication date Jan 10, 2008
- Karen Darbinyan
- G11 - INFORMATION STORAGE
Information Patent Application
Input-output device testing
- Publication number 20070079200
- Publication date Apr 5, 2007
- Sassan Tabatabaei
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN-SELF-TEST AND SELF-REPAIR METHODS AND DEVICES FOR COMPUTER...
- Publication number 20020019957
- Publication date Feb 14, 2002
- AGERE SYSTEMS GUARDIAN CORP.
- FRANK P. HIGGINS
- G11 - INFORMATION STORAGE

Yervant Zorian

Person

Patents Grantslast 30 patents

Embedded memory transparent in-system built-in self-test

On-chip memory diagnostics

Detection of address errors in memory devices using multi-segment e...

Method and apparatus for SOC with optimal RSMA

FinFET-based memory testing using multiple read operations

FinFET-based memory testing using multiple read operations

Testing electronic memories based on fault and test algorithm perio...

Periodic signal measurement using statistical sampling

Generation of memory structural model based on memory layout

Memory hard macro partition optimization for testing embedded memories

Determining a desirable number of segments for a multi-segment sing...

Detecting random telegraph noise induced failures in an electronic...

Various methods and apparatuses for effective yield enhancement of...

Architecture, system and method for compressing repair data in an i...

Methods and apparatuses for external voltage test methodology of in...

Various methods and apparatuses for memory modeling using a structu...

Architecture, system and method for compressing repair data in an i...

Various methods and apparatuses for effective yield enhancement of...

Methods and apparatuses for external test methodology and initializ...

Methods and apparatuses for external voltage test of input-output c...

System and method for repairing a memory

Memory modeling using an intermediate level structural description

System and method for verifying IP integrity in system-on-chip (SOC...

Methods and apparatuses for external delay test of input-output cir...

Input-output device testing

Methods and apparatuses that reduce the size of a repair data conta...

System and method for repairing a memory

Method and apparatus for a command based bist for testing memories

Apparatus and method to generate a repair signature

Apparatus, method, and system to allocate redundant components with...

Patents Applicationslast 30 patents

BUILT-IN SELF-TEST CIRCUIT FOR ROW HAMMERING IN MEMORY

EMBEDDED MEMORY TRANSPARENT IN-SYSTEM BUILT-IN SELF-TEST

FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS

Method and Apparatus for SOC with Optimal RSMA

FinFET-Based Memory Testing Using Multiple Read Operations

Periodic Signal Measurement Using Statistical Sampling

TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIO...

Generation of Memory Structural Model Based on Memory Layout

Determining A Desirable Number Of Segments For A Multi-Segment Sing...

MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES

DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC...

TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIO...

Architecture, System And Method For Compressing Repair Data In An I...

VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF...

VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTU...

System and Method for Repairing a Memory

Architecture, System and Method for Compressing Repair Data in an I...

Input-output device testing

BUILT-IN-SELF-TEST AND SELF-REPAIR METHODS AND DEVICES FOR COMPUTER...