Yeuk Yin MONG

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Hong Kong, HK

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Patents Grantslast 30 patents

Information Patent Grant
Integrated stacked ESD network in trench for trench DMOS
- Patent number 11,380,675
- Issue date Jul 5, 2022
- Yeuk Yin Mong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
VDMOS having shielding gate electrodes in trenches and method of ma...
- Patent number 9,704,986
- Issue date Jul 11, 2017
- International Onizuka Electronics Limited
- Mau Lam Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar mosfets and methods of fabrication, charge retention
- Patent number 9,466,707
- Issue date Oct 11, 2016
- Mau Lam Lai
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED STACKED ESD NETWORK IN TRENCH FOR TRENCH DMOS
- Publication number 20200098744
- Publication date Mar 26, 2020
- Yeuk Yin Mong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VDMOS AND METHOD FOR MAKING THE SAME
- Publication number 20170104095
- Publication date Apr 13, 2017
- International Onizuka Electronics Limited
- Mau Lam Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLANAR MOSFETS AND METHODS OF FABRICATION, CHARGE RETENTION
- Publication number 20150200290
- Publication date Jul 16, 2015
- Mau Lam Lai
- H01 - BASIC ELECTRIC ELEMENTS