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Yew Fatt Kok
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Penang, MY
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Patents Grants
last 30 patents
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Patent Grant
Clock signal networks for structured ASIC devices
Patent number
9,225,335
Issue date
Dec 29, 2015
Altera Corporation
Chooi Pei Lim
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Clock signal networks for structured ASIC devices
Patent number
8,595,658
Issue date
Nov 26, 2013
Altera Corporation
Chooi Pei Lim
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Techniques for precision biasing output driver for a calibrated on-...
Patent number
7,679,397
Issue date
Mar 16, 2010
Altera Corporation
Yew Fatt Kok
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Patents Applications
last 30 patents
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Patent Application
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
Publication number
20140077839
Publication date
Mar 20, 2014
Altera Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Clock signal networks for structured ASIC devices
Publication number
20060267661
Publication date
Nov 30, 2006
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING