Ygal Arbel

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory controller to perform in-line data processing and efficientl...
- Patent number 12,346,585
- Issue date Jul 1, 2025
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network-on-chip architecture for handling different data sizes
- Patent number 12,244,518
- Issue date Mar 4, 2025
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Chip bump interface compatible with different orientations and type...
- Patent number 12,237,287
- Issue date Feb 25, 2025
- Xilinx, Inc.
- Ygal Arbel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC with adaptive chip-to-chip interface to support different chip-t...
- Patent number 12,066,969
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with reduced latency transaction scheduling
- Patent number 12,045,502
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to transport memory mapped traffic amongst inte...
- Patent number 12,019,576
- Issue date Jun 25, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-use chip-to-chip interface
- Patent number 11,892,966
- Issue date Feb 6, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Localized NoC switching interconnect for high bandwidth interfaces
- Patent number 11,832,035
- Issue date Nov 28, 2023
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip bump interface compatible with different orientations and type...
- Patent number 11,784,149
- Issue date Oct 10, 2023
- Xilinx, Inc.
- Ygal Arbel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NoC relaxed write order scheme
- Patent number 11,714,779
- Issue date Aug 1, 2023
- Xilinx, Inc.
- Abbas Morshed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip having multiple circuits and memory controller in se...
- Patent number 11,709,624
- Issue date Jul 25, 2023
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand packetization for a chip-to-chip interface
- Patent number 11,636,061
- Issue date Apr 25, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-based virtual-to-physical address translation for programm...
- Patent number 11,327,899
- Issue date May 10, 2022
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 11,263,169
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Ian Andrew Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto-precharge management in a controller
- Patent number 10,991,417
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 10,838,908
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-based virtual-to-physical address translation for programm...
- Patent number 10,719,452
- Issue date Jul 21, 2020
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation look-aside buffer prefetch initiated by bus master
- Patent number 10,713,190
- Issue date Jul 14, 2020
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
End-to-end quality-of-service in a network-on-chip
- Patent number 10,673,745
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive quality of service control circuit
- Patent number 10,481,944
- Issue date Nov 19, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth chip-to-chip interface using HBM physical interface
- Patent number 10,410,694
- Issue date Sep 10, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline ECC function for system-on-chip
- Patent number 10,346,346
- Issue date Jul 9, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visualizing operation of a memory controller
- Patent number 10,290,287
- Issue date May 14, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling exclusive access using supplemental transaction identif...
- Patent number 10,176,131
- Issue date Jan 8, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing memory in a multiprocessor system
- Patent number 9,990,131
- Issue date Jun 5, 2018
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system network controller with interface to programmable...
- Patent number 9,934,185
- Issue date Apr 3, 2018
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridging inter-bus communications
- Patent number 9,720,868
- Issue date Aug 1, 2017
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system display controller interface to programmable logic
- Patent number 9,721,528
- Issue date Aug 1, 2017
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits for and methods of enabling the access to data
- Patent number 9,558,129
- Issue date Jan 31, 2017
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error protection for bus interconnect circuits
- Patent number 9,529,686
- Issue date Dec 27, 2016
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
- Publication number 20250202838
- Publication date Jun 19, 2025
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...
- Publication number 20250167152
- Publication date May 22, 2025
- Xilinx, Inc.
- Ygal ARBEL
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECT CIRCUITRY FOR MULTI-CHANNEL AND MULTI-REQUESTER MEMORY...
- Publication number 20250077116
- Publication date Mar 6, 2025
- Xilinx, Inc.
- Ygal ARBEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE WITH DESTINATION VIRTUALIZATION
- Publication number 20250068583
- Publication date Feb 27, 2025
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...
- Publication number 20240411715
- Publication date Dec 12, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER CRYPTOGRAPHIC DATA QUANTIZATION USING A CACHE
- Publication number 20240333473
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Abbas MORSHED
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
KEY MANAGEMENT SYSTEM
- Publication number 20240291635
- Publication date Aug 29, 2024
- Xilinx, Inc.
- Abbas MORSHED
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM CONTROLLER WITH IN-LINE ECC
- Publication number 20240281325
- Publication date Aug 22, 2024
- Xilinx, Inc.
- Ygal ARBEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20240176758
- Publication date May 30, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER TO PERFORM IN-LINE DATA PROCESSING AND EFFICIENTL...
- Publication number 20240143206
- Publication date May 2, 2024
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT TRANSACTION REDUNDANCY
- Publication number 20240111693
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods to Transport Memory Mapped Traffic amongst inte...
- Publication number 20240045822
- Publication date Feb 8, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH A PREPROCESSOR
- Publication number 20240020058
- Publication date Jan 18, 2024
- Xilinx, Inc.
- Ygal ARBEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...
- Publication number 20240014161
- Publication date Jan 11, 2024
- Xilinx, Inc.
- Ygal ARBEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM-ON-CHIP HAVING MULTIPLE CIRCUITS AND MEMORY CONTROLLER IN SE...
- Publication number 20230376248
- Publication date Nov 23, 2023
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
- Publication number 20230370392
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE
- Publication number 20230244628
- Publication date Aug 3, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20230141709
- Publication date May 11, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE
- Publication number 20230066736
- Publication date Mar 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES
- Publication number 20220337923
- Publication date Oct 20, 2022
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOC RELAXED WRITE ORDER SCHEME
- Publication number 20210303508
- Publication date Sep 30, 2021
- Xilinx, Inc.
- Abbas MORSHED
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20210303509
- Publication date Sep 30, 2021
- Xilinx, Inc.
- Ian Andrew SWARBRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20200026684
- Publication date Jan 23, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION FOR PROGRAMM...
- Publication number 20190391929
- Publication date Dec 26, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUBSYSTEM FOR SYSTEM-ON-CHIP
- Publication number 20190250853
- Publication date Aug 15, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
END-TO-END QUALITY-OF-SERVICE IN A NETWORK-ON-CHIP
- Publication number 20190238453
- Publication date Aug 1, 2019
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INLINE ECC FUNCTION FOR SYSTEM-ON-CHIP
- Publication number 20190196901
- Publication date Jun 27, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE QUALITY OF SERVICE CONTROL CIRCUIT
- Publication number 20190050252
- Publication date Feb 14, 2019
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM NETWORK CONTROLLER WITH INTERFACE TO PROGRAMMABLE...
- Publication number 20160203096
- Publication date Jul 14, 2016
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM DISPLAY CONTROLLER INTERFACE TO PROGRAMMABLE LOGIC
- Publication number 20160133225
- Publication date May 12, 2016
- Xilinx, Inc.
- Ygal Arbel
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Person

Patents Grantslast 30 patents

Memory controller to perform in-line data processing and efficientl...

Network-on-chip architecture for handling different data sizes

Chip bump interface compatible with different orientations and type...

IC with adaptive chip-to-chip interface to support different chip-t...

Memory controller with reduced latency transaction scheduling

Systems and methods to transport memory mapped traffic amongst inte...

Multi-use chip-to-chip interface

Localized NoC switching interconnect for high bandwidth interfaces

Chip bump interface compatible with different orientations and type...

NoC relaxed write order scheme

System-on-chip having multiple circuits and memory controller in se...

On-demand packetization for a chip-to-chip interface

Hardware-based virtual-to-physical address translation for programm...

Configurable network-on-chip for a programmable device

Auto-precharge management in a controller

Configurable network-on-chip for a programmable device

Hardware-based virtual-to-physical address translation for programm...

Translation look-aside buffer prefetch initiated by bus master

End-to-end quality-of-service in a network-on-chip

Adaptive quality of service control circuit

High bandwidth chip-to-chip interface using HBM physical interface

Inline ECC function for system-on-chip

Visualizing operation of a memory controller

Controlling exclusive access using supplemental transaction identif...

Managing memory in a multiprocessor system

Processing system network controller with interface to programmable...

Bridging inter-bus communications

Processing system display controller interface to programmable logic

Circuits for and methods of enabling the access to data

Error protection for bus interconnect circuits

Patents Applicationslast 30 patents

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...

INTERCONNECT CIRCUITRY FOR MULTI-CHANNEL AND MULTI-REQUESTER MEMORY...

NETWORK-ON-CHIP ARCHITECTURE WITH DESTINATION VIRTUALIZATION

IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...

MEMORY CONTROLLER CRYPTOGRAPHIC DATA QUANTIZATION USING A CACHE

KEY MANAGEMENT SYSTEM

DRAM CONTROLLER WITH IN-LINE ECC

MULTI-USE CHIP-TO-CHIP INTERFACE

MEMORY CONTROLLER TO PERFORM IN-LINE DATA PROCESSING AND EFFICIENTL...

INTEGRATED CIRCUIT TRANSACTION REDUNDANCY

Systems and Methods to Transport Memory Mapped Traffic amongst inte...

MEMORY CONTROLLER WITH A PREPROCESSOR

CHIP BUMP INTERFACE COMPATIBLE WITH DIFFERENT ORIENTATIONS AND TYPE...

SYSTEM-ON-CHIP HAVING MULTIPLE CIRCUITS AND MEMORY CONTROLLER IN SE...

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE

MULTI-USE CHIP-TO-CHIP INTERFACE

ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE

LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES

NOC RELAXED WRITE ORDER SCHEME

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

HARDWARE-BASED VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION FOR PROGRAMM...

MEMORY SUBSYSTEM FOR SYSTEM-ON-CHIP

END-TO-END QUALITY-OF-SERVICE IN A NETWORK-ON-CHIP

INLINE ECC FUNCTION FOR SYSTEM-ON-CHIP

ADAPTIVE QUALITY OF SERVICE CONTROL CIRCUIT

PROCESSING SYSTEM NETWORK CONTROLLER WITH INTERFACE TO PROGRAMMABLE...

PROCESSING SYSTEM DISPLAY CONTROLLER INTERFACE TO PROGRAMMABLE LOGIC