Yi He

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic configuring of reliability and density of non-volatile memo...
- Patent number 11,537,511
- Issue date Dec 27, 2022
- Infineon Technologies LLC
- Amir Rochman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 9,318,373
- Issue date Apr 19, 2016
- Cypress Semiconductor Corporation
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Barrier region underlying source/drain regions for dual-bit memory...
- Patent number 9,171,936
- Issue date Oct 27, 2015
- Cypress Semiconductor Corporation
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Screening for reference cells in a memory
- Patent number 9,142,311
- Issue date Sep 22, 2015
- Cypress Semiconductor Corporation
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic trim method for non volatile memory products
- Patent number 9,129,710
- Issue date Sep 8, 2015
- Maxim Integrated Products, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-pass soft programming
- Patent number 8,995,198
- Issue date Mar 31, 2015
- Spansion LLC
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
N-channel multi-time programmable memory devices
- Patent number 8,975,685
- Issue date Mar 10, 2015
- Maxim Integrated Products, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic trim method for non-volatile memory products
- Patent number 8,630,137
- Issue date Jan 14, 2014
- Maxim Integrated Products, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 8,559,255
- Issue date Oct 15, 2013
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 8,445,966
- Issue date May 21, 2013
- Spansion LLC
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Strapping contact for charge protection
- Patent number 8,404,541
- Issue date Mar 26, 2013
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 8,264,898
- Issue date Sep 11, 2012
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Applying negative gate voltage to wordlines adjacent to wordline as...
- Patent number 7,995,386
- Issue date Aug 9, 2011
- Spansion LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 7,986,562
- Issue date Jul 26, 2011
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Thin oxide dummy tiling as charge protection
- Patent number 7,977,218
- Issue date Jul 12, 2011
- Spansion LLC
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strapping contact for charge protection
- Patent number 7,750,407
- Issue date Jul 6, 2010
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable salicide block for resistance equalization in an array
- Patent number 7,713,875
- Issue date May 11, 2010
- Spansion LLC
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 7,679,967
- Issue date Mar 16, 2010
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Deep bitline implant to avoid program disturb
- Patent number 7,671,405
- Issue date Mar 2, 2010
- Spansion LLC
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-phase wordline erasing for flash memory
- Patent number 7,626,869
- Issue date Dec 1, 2009
- Spansion LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Back-to-back NPN/PNP protection diodes
- Patent number 7,573,103
- Issue date Aug 11, 2009
- Spansion LLC
- Yi He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cycling improvement using higher erase bias
- Patent number 7,561,471
- Issue date Jul 14, 2009
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Select transistor using buried bit line from core
- Patent number 7,561,457
- Issue date Jul 14, 2009
- Spansion LLC
- Mark Randolph
- G11 - INFORMATION STORAGE
Information Patent Grant
Using implanted poly-1 to improve charging protection in dual-poly...
- Patent number 7,553,727
- Issue date Jun 30, 2009
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for protecting semiconductor devices
- Patent number 7,402,868
- Issue date Jul 22, 2008
- Spansion LLC
- Ihsan Jahed Djomehri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ramp gate erase for dual bit flash memory
- Patent number 7,319,615
- Issue date Jan 15, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Back-to-back NPN/PNP protection diodes
- Patent number 7,285,827
- Issue date Oct 23, 2007
- Spansion LLC
- Yi He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming a memory device
- Patent number 7,269,067
- Issue date Sep 11, 2007
- Spansion LLC
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory cell and methods for programming and erasing
- Patent number 7,215,577
- Issue date May 8, 2007
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for reducing the threshold voltage distribution...
- Patent number 7,170,796
- Issue date Jan 30, 2007
- Spansion LLC
- Yi He
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC CONFIGURING OF RELIABILITY AND DENSITY OF NON-VOLATILE MEMO...
- Publication number 20220043745
- Publication date Feb 10, 2022
- Infineon Technologies LLC
- Amir Rochman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PASS SOFT PROGRAMMING
- Publication number 20150103601
- Publication date Apr 16, 2015
- SPANSION LLC
- Gulzar A. KATHAWALA
- G11 - INFORMATION STORAGE
Information Patent Application
Screening for Reference Cells in a Memory
- Publication number 20140369141
- Publication date Dec 18, 2014
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
N-Channel Multi-Time Programmable Memory Devices
- Publication number 20140063958
- Publication date Mar 6, 2014
- Maxim Integrated Products, Inc.
- Yi He
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20130237022
- Publication date Sep 12, 2013
- SPANSION LLC
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20120294103
- Publication date Nov 22, 2012
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20110235412
- Publication date Sep 29, 2011
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20100240210
- Publication date Sep 23, 2010
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...
- Publication number 20100128521
- Publication date May 27, 2010
- SPANSION LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20100103732
- Publication date Apr 29, 2010
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20090161462
- Publication date Jun 25, 2009
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
- Publication number 20080279014
- Publication date Nov 13, 2008
- SPANSION LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Cycling improvement using higher erase bias
- Publication number 20080151644
- Publication date Jun 26, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Application
Thin oxide dummy tiling as charge protection
- Publication number 20080153269
- Publication date Jun 26, 2008
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20080151590
- Publication date Jun 26, 2008
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
Deep bitline implant to avoid program disturb
- Publication number 20080153274
- Publication date Jun 26, 2008
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Application
VARIABLE SALICIDE BLOCK FOR RESISTANCE EQUALIZATION IN AN ARRAY
- Publication number 20080150007
- Publication date Jun 26, 2008
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using implanted poly-1 to improve charging protection in dual-poly...
- Publication number 20080150006
- Publication date Jun 26, 2008
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20080142889
- Publication date Jun 19, 2008
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier region for memory devices
- Publication number 20080135902
- Publication date Jun 12, 2008
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
- Publication number 20080123384
- Publication date May 29, 2008
- SPANSION LLC
- Mark RANDOLPH
- G11 - INFORMATION STORAGE
Information Patent Application
RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY
- Publication number 20080037330
- Publication date Feb 14, 2008
- Spansion LLC
- Sheung-Hee Park
- G11 - INFORMATION STORAGE
Information Patent Application
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to impr...
- Publication number 20070029604
- Publication date Feb 8, 2007
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for programming a memory device
- Publication number 20070008782
- Publication date Jan 11, 2007
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory cell and methods for programming and erasing
- Publication number 20060291282
- Publication date Dec 28, 2006
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Read-only memory array with dielectric breakdown programmability
- Publication number 20060268593
- Publication date Nov 30, 2006
- Spansion LLC
- Meng Ding
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for protecting semiconductor devices
- Publication number 20060091439
- Publication date May 4, 2006
- Ihsan Jahed Djomehri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pocket implant for complementary bit disturb improvement and chargi...
- Publication number 20050153508
- Publication date Jul 14, 2005
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device and method using positive gate stress to recover over...
- Publication number 20050073886
- Publication date Apr 7, 2005
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE
Information Patent Application
Method of programming dual cell memory device to store multiple dat...
- Publication number 20040208057
- Publication date Oct 21, 2004
- Darlene G. Hamilton
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Dynamic configuring of reliability and density of non-volatile memo...

Method and apparatus for protection against process-induced charging

Barrier region underlying source/drain regions for dual-bit memory...

Screening for reference cells in a memory

Dynamic trim method for non volatile memory products

Multi-pass soft programming

N-channel multi-time programmable memory devices

Dynamic trim method for non-volatile memory products

Controlling AC disturbance while programming

Method and apparatus for protection against process-induced charging

Strapping contact for charge protection

Controlling AC disturbance while programming

Applying negative gate voltage to wordlines adjacent to wordline as...

Controlling AC disturbance while programming

Thin oxide dummy tiling as charge protection

Strapping contact for charge protection

Variable salicide block for resistance equalization in an array

Controlling AC disturbance while programming

Deep bitline implant to avoid program disturb

Multi-phase wordline erasing for flash memory

Back-to-back NPN/PNP protection diodes

Cycling improvement using higher erase bias

Select transistor using buried bit line from core

Using implanted poly-1 to improve charging protection in dual-poly...

System and method for protecting semiconductor devices

Ramp gate erase for dual bit flash memory

Back-to-back NPN/PNP protection diodes

Programming a memory device

Flash memory cell and methods for programming and erasing

Methods and systems for reducing the threshold voltage distribution...

Patents Applicationslast 30 patents

DYNAMIC CONFIGURING OF RELIABILITY AND DENSITY OF NON-VOLATILE MEMO...

MULTI-PASS SOFT PROGRAMMING

Screening for Reference Cells in a Memory

N-Channel Multi-Time Programmable Memory Devices

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

STRAPPING CONTACT FOR CHARGE PROTECTION

APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY

Cycling improvement using higher erase bias

Thin oxide dummy tiling as charge protection

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

Deep bitline implant to avoid program disturb

VARIABLE SALICIDE BLOCK FOR RESISTANCE EQUALIZATION IN AN ARRAY

Using implanted poly-1 to improve charging protection in dual-poly...

STRAPPING CONTACT FOR CHARGE PROTECTION

Barrier region for memory devices

SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE

RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to impr...

Method for programming a memory device

Flash memory cell and methods for programming and erasing

Read-only memory array with dielectric breakdown programmability

System and method for protecting semiconductor devices

Pocket implant for complementary bit disturb improvement and chargi...

Memory device and method using positive gate stress to recover over...

Method of programming dual cell memory device to store multiple dat...