Yi-Hsien Chuang

Person

Kaohsiung City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a semiconductor device with inter-layer vias
- Patent number 12,154,851
- Issue date Nov 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule check violation prediction systems and methods
- Patent number 12,106,034
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule check violation prediction systems and methods
- Patent number 12,099,793
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell layout of semiconductor device
- Patent number 12,039,251
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static voltage drop (SIR) violation prediction systems and methods
- Patent number 12,019,971
- Issue date Jun 25, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard-to-fix (HTF) design rule check (DRC) violations prediction
- Patent number 11,928,415
- Issue date Mar 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit synthesis optimization for implements on integrated circuit
- Patent number 11,900,037
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing floor plan for an integrated circuit
- Patent number 11,893,334
- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-routing congestion optimization
- Patent number 11,853,681
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing floor plan for an integrated circuit
- Patent number 11,853,675
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule check violation prediction systems and methods
- Patent number 11,816,417
- Issue date Nov 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating layout design of integrated circuit
- Patent number 11,709,987
- Issue date Jul 25, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shih-Yao Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static voltage drop (SIR) violation prediction systems and methods
- Patent number 11,604,917
- Issue date Mar 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell layout of semiconductor device
- Patent number 11,568,119
- Issue date Jan 31, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard-to-fix (HTF) design rule check (DRC) violations prediction
- Patent number 11,562,118
- Issue date Jan 24, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for fixing violation of layout
- Patent number 11,481,536
- Issue date Oct 25, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing floor plan for an integrated circuit
- Patent number 11,443,096
- Issue date Sep 13, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for diagnosing design rule check violations
- Patent number 11,443,097
- Issue date Sep 13, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Yu-Chen Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit synthesis optimization for implements on integrated circuit
- Patent number 11,347,920
- Issue date May 31, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraint determination system and method for semiconductor circuit
- Patent number 11,263,375
- Issue date Mar 1, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for layout design of structure with inter layer vias
- Patent number 11,114,376
- Issue date Sep 7, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating layout design of integrated circuit
- Patent number 11,093,681
- Issue date Aug 17, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shih-Yao Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static voltage drop (SIR) violation prediction systems and methods
- Patent number 11,087,066
- Issue date Aug 10, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning design enablement platform
- Patent number 11,017,149
- Issue date May 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule check violation prediction systems and methods
- Patent number 10,943,049
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell layout of semiconductor device
- Patent number 10,922,466
- Issue date Feb 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static voltage drop (SIR) violation prediction systems and methods
- Patent number 10,810,346
- Issue date Oct 20, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning design enablement platform
- Patent number 10,678,973
- Issue date Jun 9, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for layout design and structure with inter-layer vias
- Patent number 10,566,278
- Issue date Feb 18, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for timing optimization with detour prediction
- Patent number 10,268,795
- Issue date Apr 23, 2019
- Taiwan Semiconductor Manufacturing Company Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20240394460
- Publication date Nov 28, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS
- Publication number 20240330563
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chen Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD-TO-FIX (HTF) DESIGN RULE CHECK (DRC) VIOLATIONS PREDICTION
- Publication number 20240176945
- Publication date May 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20240135078
- Publication date Apr 25, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Post-Routing Congestion Optimization
- Publication number 20240126973
- Publication date Apr 18, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT
- Publication number 20240104285
- Publication date Mar 28, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20230385520
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20230385521
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR GENERATING LAYOUT DESIGN OF INTEGRATED CIRCUIT
- Publication number 20230325573
- Publication date Oct 12, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIH-YAO LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hard-to-Fix (HTF) Design Rule Check (DRC) Violations Prediction
- Publication number 20230229846
- Publication date Jul 20, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20230214575
- Publication date Jul 6, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL LAYOUT OF SEMICONDUCTOR DEVICE
- Publication number 20230153508
- Publication date May 18, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSPECTION METHOD AND INSPECTION PLATFORM FOR LITHOGRAPHY
- Publication number 20230131662
- Publication date Apr 27, 2023
- Industrial Technology Research Institute
- Cheng-Hsien CHEN
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS
- Publication number 20220391574
- Publication date Dec 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chen Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT
- Publication number 20220382950
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FIXING VIOLATION OF LAYOUT
- Publication number 20220366121
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT
- Publication number 20220366118
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Post-Routing Congestion Optimization
- Publication number 20220335197
- Publication date Oct 20, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20220284162
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hard-to-Fix (HTF) Design Rule Check (DRC) Violations Prediction
- Publication number 20220215149
- Publication date Jul 7, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS
- Publication number 20220164515
- Publication date May 26, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Yu-Chen Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FIXING VIOLATION OF LAYOUT
- Publication number 20220147691
- Publication date May 12, 2022
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPNAY, LTD.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Synthesis Optimization for Implements on Integrated Circuit
- Publication number 20220121798
- Publication date Apr 21, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Chun Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT
- Publication number 20220092248
- Publication date Mar 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH INTER-LAYER VIAS
- Publication number 20210384119
- Publication date Dec 9, 2021
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINT DETERMINATION SYSTEM AND METHOD FOR SEMICONDUCTOR CIRCUIT
- Publication number 20210365620
- Publication date Nov 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20210365624
- Publication date Nov 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR GENERATING LAYOUT DESIGN OF INTEGRATED CIRCUIT
- Publication number 20210357569
- Publication date Nov 18, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIH-YAO LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS
- Publication number 20210174000
- Publication date Jun 10, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL LAYOUT OF SEMICONDUCTOR DEVICE
- Publication number 20210133384
- Publication date May 6, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING

Yi-Hsien Chuang

Person

Patents Grantslast 30 patents

Method of forming a semiconductor device with inter-layer vias

Rule check violation prediction systems and methods

Rule check violation prediction systems and methods

Cell layout of semiconductor device

Static voltage drop (SIR) violation prediction systems and methods

Hard-to-fix (HTF) design rule check (DRC) violations prediction

Circuit synthesis optimization for implements on integrated circuit

Method for optimizing floor plan for an integrated circuit

Post-routing congestion optimization

Method for optimizing floor plan for an integrated circuit

Rule check violation prediction systems and methods

Method and system for generating layout design of integrated circuit

Static voltage drop (SIR) violation prediction systems and methods

Cell layout of semiconductor device

Hard-to-fix (HTF) design rule check (DRC) violations prediction

Method and system for fixing violation of layout

Method for optimizing floor plan for an integrated circuit

System and method for diagnosing design rule check violations

Circuit synthesis optimization for implements on integrated circuit

Constraint determination system and method for semiconductor circuit

System for layout design of structure with inter layer vias

Method and system for generating layout design of integrated circuit

Static voltage drop (SIR) violation prediction systems and methods

Machine-learning design enablement platform

Rule check violation prediction systems and methods

Cell layout of semiconductor device

Static voltage drop (SIR) violation prediction systems and methods

Machine-learning design enablement platform

Method for layout design and structure with inter-layer vias

Method and system for timing optimization with detour prediction

Patents Applicationslast 30 patents

RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS

HARD-TO-FIX (HTF) DESIGN RULE CHECK (DRC) VIOLATIONS PREDICTION

Circuit Synthesis Optimization for Implements on Integrated Circuit

Post-Routing Congestion Optimization

METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

METHOD AND SYSTEM FOR GENERATING LAYOUT DESIGN OF INTEGRATED CIRCUIT

Hard-to-Fix (HTF) Design Rule Check (DRC) Violations Prediction

STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS

CELL LAYOUT OF SEMICONDUCTOR DEVICE

INSPECTION METHOD AND INSPECTION PLATFORM FOR LITHOGRAPHY

SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS

METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT

METHOD AND SYSTEM FOR FIXING VIOLATION OF LAYOUT

METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT

Post-Routing Congestion Optimization

Circuit Synthesis Optimization for Implements on Integrated Circuit

Hard-to-Fix (HTF) Design Rule Check (DRC) Violations Prediction

SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS

METHOD AND SYSTEM FOR FIXING VIOLATION OF LAYOUT

Circuit Synthesis Optimization for Implements on Integrated Circuit

METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT

METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH INTER-LAYER VIAS

CONSTRAINT DETERMINATION SYSTEM AND METHOD FOR SEMICONDUCTOR CIRCUIT

STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS

METHOD AND SYSTEM FOR GENERATING LAYOUT DESIGN OF INTEGRATED CIRCUIT

DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS

CELL LAYOUT OF SEMICONDUCTOR DEVICE