Yi-Xiao Ding

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Driver resizing using a transition-based pin capacitance increase m...
- Patent number 11,868,695
- Issue date Jan 9, 2024
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pruning redundant buffering solutions using fast timing models
- Patent number 11,675,956
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based clustering for clock tree synthesis
- Patent number 11,645,441
- Issue date May 9, 2023
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grouping cells in cell library based on clustering
- Patent number 11,625,525
- Issue date Apr 11, 2023
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching power aware driver resizing by considering net activity i...
- Patent number 11,526,650
- Issue date Dec 13, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pruning of buffering candidates for improved efficiency of evaluation
- Patent number 11,520,959
- Issue date Dec 6, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell-width aware buffer insertion technique for narrow channels
- Patent number 11,514,222
- Issue date Nov 29, 2022
- Cadence Design Systems, Inc.
- Sheng-En David Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Anti-spoofing for contactless fingerprint readers
- Patent number 11,514,708
- Issue date Nov 29, 2022
- THALES DIS FRANCE SAS
- Yi Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering algorithm with maximum cost constraint
- Patent number 11,347,923
- Issue date May 31, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based prediction method for iterative clustering d...
- Patent number 11,244,099
- Issue date Feb 8, 2022
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment based on wirelength threshold
- Patent number 11,132,489
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment and routing based on resistance or capacitance cha...
- Patent number 11,080,457
- Issue date Aug 3, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Track assignment by dynamic programming
- Patent number 11,030,378
- Issue date Jun 8, 2021
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer insertion technique to consider edge spacing and stack via d...
- Patent number 10,963,620
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified improvement scoring calculation for rebuffering an integrat...
- Patent number 10,936,777
- Issue date Mar 2, 2021
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment technique to improve timing in integrated circuit...
- Patent number 10,860,764
- Issue date Dec 8, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing using multi-panel track assignment
- Patent number 10,706,201
- Issue date Jul 7, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on parallel run length rules
- Patent number 10,685,164
- Issue date Jun 16, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing track assignment
- Patent number 10,509,878
- Issue date Dec 17, 2019
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of cells in a multi-level routing tree
- Patent number 10,402,533
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS
- Publication number 20220318480
- Publication date Oct 6, 2022
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTI-SPOOFING FOR CONTACTLESS FINGERPRINT READERS
- Publication number 20220284210
- Publication date Sep 8, 2022
- THALES DIS USA, INC
- Yi DING
- G06 - COMPUTING CALCULATING COUNTING

Yi-Xiao Ding

Person

Patents Grantslast 30 patents

Driver resizing using a transition-based pin capacitance increase m...

Pruning redundant buffering solutions using fast timing models

Machine-learning based clustering for clock tree synthesis

Grouping cells in cell library based on clustering

Switching power aware driver resizing by considering net activity i...

Pruning of buffering candidates for improved efficiency of evaluation

Cell-width aware buffer insertion technique for narrow channels

Anti-spoofing for contactless fingerprint readers

Buffering algorithm with maximum cost constraint

Machine-learning based prediction method for iterative clustering d...

Layer assignment based on wirelength threshold

Layer assignment and routing based on resistance or capacitance cha...

Track assignment by dynamic programming

Buffer insertion technique to consider edge spacing and stack via d...

Unified improvement scoring calculation for rebuffering an integrat...

Layer assignment technique to improve timing in integrated circuit...

Circuit design routing using multi-panel track assignment

Circuit design routing based on parallel run length rules

Systems and methods for routing track assignment

Placement of cells in a multi-level routing tree

Patents Applicationslast 30 patents

PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS

ANTI-SPOOFING FOR CONTACTLESS FINGERPRINT READERS