Ying-Chun WEI

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Hsinchu City, TW

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Patents Grantslast 30 patents

Information Patent Grant
Full adder circuits with reduced delay
- Patent number 10,620,915
- Issue date Apr 14, 2020
- Mediatek Inc.
- Ying-Chun Wei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay cell in a standard cell library
- Patent number 9,705,484
- Issue date Jul 11, 2017
- Mediatek Inc.
- Ying-Chun Wei
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
POWER LEVEL DETECTION CIRCUIT AND TWO-STAGE POWER DOMAIN CIRCUIT
- Publication number 20240369605
- Publication date Nov 7, 2024
- MEDIATEK INC.
- Jen-Hang YANG
- G01 - MEASURING TESTING
Information Patent Application
FULL ADDER CIRCUITS WITH REDUCED DELAY
- Publication number 20200065065
- Publication date Feb 27, 2020
- MEDIATEK INC.
- Ying-Chun WEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY CELL IN A STANDARD CELL LIBRARY
- Publication number 20160380624
- Publication date Dec 29, 2016
- MEDIATEK INC.
- Ying-Chun WEI
- G06 - COMPUTING CALCULATING COUNTING