Yip Seng Low

Person

Thornhill, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip with patterned underbump metallization and polym...
- Patent number 11,335,659
- Issue date May 17, 2022
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit board with via trace connection and method of making the same
- Patent number 9,793,199
- Issue date Oct 17, 2017
- ATI Technologies ULC
- Andrew K W Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with patterned underbump metallization and polym...
- Patent number 9,576,923
- Issue date Feb 21, 2017
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder mask with anchor structures
- Patent number 8,772,083
- Issue date Jul 8, 2014
- ATI Technologies ULC
- Andrew K W Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Face-to-face (F2F) hybrid structure for an integrated circuit
- Patent number 8,637,983
- Issue date Jan 28, 2014
- ATI Technologies ULC
- Liane Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit board component shim structure
- Patent number 8,564,122
- Issue date Oct 22, 2013
- Advanced Micro Devices, Inc.
- Neil R. McLellan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing substrates having asymmetric buildup layers
- Patent number 8,298,945
- Issue date Oct 30, 2012
- ATI Technologies ULC
- Andrew Leung
- B32 - LAYERED PRODUCTS
Information Patent Grant
Conductor bump method and apparatus
- Patent number 8,294,266
- Issue date Oct 23, 2012
- Advanced Micro Devices, Inc.
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductor bump method and apparatus
- Patent number 7,906,424
- Issue date Mar 15, 2011
- Advanced Micro Devices, Inc.
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...
- Publication number 20170110428
- Publication date Apr 20, 2017
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...
- Publication number 20150279794
- Publication date Oct 1, 2015
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP DEVICE WITH VENTED LID
- Publication number 20130258610
- Publication date Oct 3, 2013
- Jianguo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HEATSINK INTERPOSER
- Publication number 20130147026
- Publication date Jun 13, 2013
- ATI Technologies ULC
- Roden R. TOPACIO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT BOARD COMPONENT SHIM STRUCTURE
- Publication number 20130147012
- Publication date Jun 13, 2013
- Neil R. McLellan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER
- Publication number 20130113084
- Publication date May 9, 2013
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER MASK WITH ANCHOR STRUCTURES
- Publication number 20130062786
- Publication date Mar 14, 2013
- Andrew KW Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT BOARD WITH VIA TRACE CONNECTION AND METHOD OF MAKING THE SAME
- Publication number 20120120615
- Publication date May 17, 2012
- Andrew K.W. Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
- Publication number 20110225813
- Publication date Sep 22, 2011
- ATI Technologies ULC
- Andrew Leung
- B32 - LAYERED PRODUCTS
Information Patent Application
Circuit Board with Via Trace Connection and Method of Making the Same
- Publication number 20110147061
- Publication date Jun 23, 2011
- Andrew K.W. Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTOR BUMP METHOD AND APPARATUS
- Publication number 20110133338
- Publication date Jun 9, 2011
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Chip with Stair Arrangement Bump Structures
- Publication number 20110057307
- Publication date Mar 10, 2011
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
- Publication number 20110024898
- Publication date Feb 3, 2011
- ATI Technologies ULC
- Andrew Leung
- B32 - LAYERED PRODUCTS
Information Patent Application
FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT
- Publication number 20100155938
- Publication date Jun 24, 2010
- ATI Technologies ULC
- Liane Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Semiconductor Chip Package
- Publication number 20100102457
- Publication date Apr 29, 2010
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductor Bump Method and Apparatus
- Publication number 20090032940
- Publication date Feb 5, 2009
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS

Yip Seng Low

Person

Patents Grantslast 30 patents

Semiconductor chip with patterned underbump metallization and polym...

Circuit board with via trace connection and method of making the same

Semiconductor chip with patterned underbump metallization and polym...

Solder mask with anchor structures

Face-to-face (F2F) hybrid structure for an integrated circuit

Circuit board component shim structure

Method of manufacturing substrates having asymmetric buildup layers

Conductor bump method and apparatus

Conductor bump method and apparatus

Patents Applicationslast 30 patents

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...

SEMICONDUCTOR CHIP DEVICE WITH VENTED LID

HEATSINK INTERPOSER

CIRCUIT BOARD COMPONENT SHIM STRUCTURE

SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER

SOLDER MASK WITH ANCHOR STRUCTURES

CIRCUIT BOARD WITH VIA TRACE CONNECTION AND METHOD OF MAKING THE SAME

METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS

Circuit Board with Via Trace Connection and Method of Making the Same

CONDUCTOR BUMP METHOD AND APPARATUS

Semiconductor Chip with Stair Arrangement Bump Structures

METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS

FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT

Hybrid Semiconductor Chip Package

Conductor Bump Method and Apparatus