Yirng-An Chen

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Latch modeling technique for formal verification
- Patent number 7,254,793
- Issue date Aug 7, 2007
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC behavior analysis system
- Patent number 7,079,997
- Issue date Jul 18, 2006
- Novas Software, Inc.
- Yu-Chin Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for characterizing simulated circuit logic and behavior
- Patent number 7,031,899
- Issue date Apr 18, 2006
- Novas Software, Inc.
- Yu-Chin Hsu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Latch modeling technique for formal verification
- Publication number 20060190870
- Publication date Aug 24, 2006
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING