Yizhou LIN

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method to reduce full-chip timing violation through time budgeting...
- Patent number 10,956,639
- Issue date Mar 23, 2021
- ARCADIA INNOVATION INCORPORATED
- Yizhou Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-instantiation time budgeting for integrated circuit design an...
- Patent number 10,810,344
- Issue date Oct 20, 2020
- Hongchang Liang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-INSTANTIATION TIME BUDGETING FOR INTEGRATED CIRCUIT DESIGN AN...
- Publication number 20200311224
- Publication date Oct 1, 2020
- Hongchang LIANG
- G06 - COMPUTING CALCULATING COUNTING