Yoav Harel

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,676,239
- Issue date Jun 13, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 11,620,256
- Issue date Apr 4, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,113,784
- Issue date Sep 7, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource load balancing based on usage and power limits
- Patent number 10,983,581
- Issue date Apr 20, 2021
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sampler load balancing
- Patent number 9,489,707
- Issue date Nov 8, 2016
- Intel Corporation
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible filter logic for multi-mode filtering of graphical texture...
- Patent number 9,367,948
- Issue date Jun 14, 2016
- Intel Corporation
- Liang Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimum-maximum filtering of graphical texture data
- Patent number 9,355,490
- Issue date May 31, 2016
- Intel Corporation
- Liang Peng
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES
- Publication number 20240231621
- Publication date Jul 11, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES
- Publication number 20240134527
- Publication date Apr 25, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ SAMPLER FEEDBACK TECHNOLOGY
- Publication number 20230137408
- Publication date May 4, 2023
- Intel Corporation
- Daniel Johnston
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER EXECUTION OF GRAPHICS PROCESSING UNIT TEXTURE SAMPLER...
- Publication number 20230111571
- Publication date Apr 13, 2023
- Intel Corporation
- Carlos Nava Rodriguez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NATIVE SAMPLER FEEDBACK TECHNOLOGY
- Publication number 20230094067
- Publication date Mar 30, 2023
- Intel Corporation
- Daniel Johnston
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CACHING OF RESOURCE STATE FOR A SHARED FUNCTION OF A THRE...
- Publication number 20230094696
- Publication date Mar 30, 2023
- Intel Corporation
- Carlos Nava Rodriguez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING
- Publication number 20230101654
- Publication date Mar 30, 2023
- Intel Corporation
- Carlos Nava Rodriguez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220261347
- Publication date Aug 18, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220179787
- Publication date Jun 9, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210374897
- Publication date Dec 2, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210035258
- Publication date Feb 4, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOURCE LOAD BALANCING BASED ON USAGE AND POWER LIMITS
- Publication number 20190204894
- Publication date Jul 4, 2019
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PRE-DECOMPRESSION FILTERING OF COMPRESSED...
- Publication number 20190096095
- Publication date Mar 28, 2019
- KIRAN C. VEERNAPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIPMAP COMPRESSION
- Publication number 20150279055
- Publication date Oct 1, 2015
- NIKOS KABURLASOS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MINIMUM-MAXIMUM FILTERING OF GRAPHICAL TEXTURE DATA
- Publication number 20150130819
- Publication date May 14, 2015
- Liang Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE FILTER LOGIC FOR MULTI-MODE FILTERING OF GRAPHICAL TEXTURE...
- Publication number 20150130818
- Publication date May 14, 2015
- Liang Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAMPLER LOAD BALANCING
- Publication number 20150091919
- Publication date Apr 2, 2015
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Sparse optimizations for a matrix accelerator architecture

Systems and methods for improving cache efficiency and utilization

Sparse optimizations for a matrix accelerator architecture

Resource load balancing based on usage and power limits

Sampler load balancing

Flexible filter logic for multi-mode filtering of graphical texture...

Minimum-maximum filtering of graphical texture data

Patents Applicationslast 30 patents

VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES

VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

READ SAMPLER FEEDBACK TECHNOLOGY

OUT-OF-ORDER EXECUTION OF GRAPHICS PROCESSING UNIT TEXTURE SAMPLER...

NATIVE SAMPLER FEEDBACK TECHNOLOGY

EFFICIENT CACHING OF RESOURCE STATE FOR A SHARED FUNCTION OF A THRE...

DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE

RESOURCE LOAD BALANCING BASED ON USAGE AND POWER LIMITS

APPARATUS AND METHOD FOR PRE-DECOMPRESSION FILTERING OF COMPRESSED...

MIPMAP COMPRESSION

MINIMUM-MAXIMUM FILTERING OF GRAPHICAL TEXTURE DATA

FLEXIBLE FILTER LOGIC FOR MULTI-MODE FILTERING OF GRAPHICAL TEXTURE...

SAMPLER LOAD BALANCING