Yogendra Ranade

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Patent number 7,354,790
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Construction to improve thermal performance and reduce die backside...
- Patent number 7,145,232
- Issue date Dec 5, 2006
- LSI Logic Corporation
- Rajagopalan Parthasarathy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stiffener design
- Patent number 6,825,066
- Issue date Nov 30, 2004
- LSI Logic Corporation
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Characteristic impedance equalizer and an integrated circuit packag...
- Patent number 6,759,921
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Anand Govind
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Integrated circuit package and method with an electrical component...
- Publication number 20070013068
- Publication date Jan 18, 2007
- LSI Logic Corporation
- Yogendra Ranade
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Method and apparatus for avoiding dicing chip-outs in integrated ci...
- Publication number 20060160269
- Publication date Jul 20, 2006
- LSI Logic Corporation
- Parthasarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for forming angled vias in an integrated circu...
- Publication number 20060131283
- Publication date Jun 22, 2006
- LSI Logic Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Construction to improve thermal performance and reduce die backside...
- Publication number 20060071327
- Publication date Apr 6, 2006
- Rajagopalan Parthasarathy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low temperature PB-free processing for semiconductor devices
- Publication number 20060043603
- Publication date Mar 2, 2006
- LSI Logic Corporation
- Yogendra Ranade
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Stiffener design
- Publication number 20040105241
- Publication date Jun 3, 2004
- Yogendra Ranade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip chip electrical test yields by countering substrate die area c...
- Publication number 20040099962
- Publication date May 27, 2004
- Sarathy Rajagopalan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Yogendra Ranade

Person

Patents Grantslast 30 patents

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Construction to improve thermal performance and reduce die backside...

Stiffener design

Characteristic impedance equalizer and an integrated circuit packag...

Patents Applicationslast 30 patents

Integrated circuit package and method with an electrical component...

Method and apparatus for avoiding dicing chip-outs in integrated ci...

Method and apparatus for forming angled vias in an integrated circu...

Construction to improve thermal performance and reduce die backside...

Low temperature PB-free processing for semiconductor devices

Stiffener design

Flip chip electrical test yields by countering substrate die area c...