Yongseok Cheon

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for generating a variation-tolerant clock-tree...
- Patent number 7,546,567
- Issue date Jun 9, 2009
- Synopsys, Inc.
- Yongseok Cheon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partitioning an integrated circuit chip
- Patent number 7,260,802
- Issue date Aug 21, 2007
- Synopsys, Inc.
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing power consumption in an integrate...
- Patent number 7,257,782
- Issue date Aug 14, 2007
- Synopsys, Inc.
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for generating a variation-tolerant clock-tree...
- Publication number 20080168412
- Publication date Jul 10, 2008
- Yongseok Cheon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for partitioning an integrated circuit chip
- Publication number 20060101365
- Publication date May 11, 2006
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing power consumption in an integrate...
- Publication number 20060090153
- Publication date Apr 27, 2006
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING