Yoni Landau

Person

Or-Aqiva, IL

People

Patents Grantslast 30 patents

Information Patent Grant
High accuracy time stamping for multi-lane ports
- Patent number 11,711,159
- Issue date Jul 25, 2023
- Intel Corporation
- Mark Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,546,241
- Issue date Jan 3, 2023
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High accuracy time stamping for multi-lane ports
- Patent number 11,265,096
- Issue date Mar 1, 2022
- Intel Corporation
- Mark Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for link partner error reporting
- Patent number 11,190,208
- Issue date Nov 30, 2021
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technologies for timestamping with error correction
- Patent number 11,153,191
- Issue date Oct 19, 2021
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for link partner error reporting
- Patent number 10,924,132
- Issue date Feb 16, 2021
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technologies for ethernet link robustness for deep sleep low power...
- Patent number 9,722,717
- Issue date Aug 1, 2017
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20220150149
- Publication date May 12, 2022
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS
- Publication number 20210152271
- Publication date May 20, 2021
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Techniques For Link Partner Error Reporting
- Publication number 20200321978
- Publication date Oct 8, 2020
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS
- Publication number 20190273571
- Publication date Sep 5, 2019
- Intel Corporation
- Mark BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR LINK PARTNER ERROR REPORTING
- Publication number 20190215008
- Publication date Jul 11, 2019
- Intel Corporation
- Adee Ofir Ran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION
- Publication number 20190044839
- Publication date Feb 7, 2019
- Intel Corporation
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR ETHERNET LINK ROBUSTNESS FOR DEEP SLEEP LOW POWER...
- Publication number 20160182175
- Publication date Jun 23, 2016
- Yoni Landau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Yoni Landau

Person

Patents Grantslast 30 patents

High accuracy time stamping for multi-lane ports

Technologies for timestamping with error correction

High accuracy time stamping for multi-lane ports

Techniques for link partner error reporting

Technologies for timestamping with error correction

Techniques for link partner error reporting

Technologies for ethernet link robustness for deep sleep low power...

Patents Applicationslast 30 patents

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS

Techniques For Link Partner Error Reporting

HIGH ACCURACY TIME STAMPING FOR MULTI-LANE PORTS

TECHNIQUES FOR LINK PARTNER ERROR REPORTING

TECHNOLOGIES FOR TIMESTAMPING WITH ERROR CORRECTION

TECHNOLOGIES FOR ETHERNET LINK ROBUSTNESS FOR DEEP SLEEP LOW POWER...