Yoshiharu Mitono

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Gate array semiconductor integrated circuit
- Patent number 4,868,630
- Issue date Sep 19, 1989
- Fujitsu Limited
- Tetsu Tanizawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with a means for discharging carriers
- Patent number 4,613,887
- Issue date Sep 23, 1986
- Fujitsu Limited
- Takeshi Fukuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor gate array device having an improved interconnection...
- Patent number 4,564,773
- Issue date Jan 14, 1986
- Fujitsu Limited
- Tetsu Tanizawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having predetermined outer to inner cell pitch r...
- Patent number 4,523,106
- Issue date Jun 11, 1985
- Fujitsu Limited
- Tetsu Tanizawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit manufactured by master slice method
- Patent number 4,499,484
- Issue date Feb 12, 1985
- Fujitsu Limited
- Tetsu Tanizawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic circuit with improved switching
- Patent number 4,449,063
- Issue date May 15, 1984
- Fujitsu Limited
- Hitoshi Ohmichi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Schmitt trigger circuit with low input current
- Patent number 4,409,495
- Issue date Oct 11, 1983
- Fujitsu Limited
- Hiromu Enomoto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure for and method of manufacturing a semiconductor device by...
- Patent number 4,388,755
- Issue date Jun 21, 1983
- Fujitsu Limited
- Hiromu Enomoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 4,276,556
- Issue date Jun 30, 1981
- Fujitsu Limited
- Hiromu Enomoto
- H01 - BASIC ELECTRIC ELEMENTS

Yoshiharu Mitono

Person

Patents Grantslast 30 patents

Gate array semiconductor integrated circuit

Semiconductor device with a means for discharging carriers

Semiconductor gate array device having an improved interconnection...

Integrated circuit having predetermined outer to inner cell pitch r...

Integrated circuit manufactured by master slice method

Logic circuit with improved switching

Schmitt trigger circuit with low input current

Structure for and method of manufacturing a semiconductor device by...

Semiconductor device