Yoshihito Morishita

Person

Shibuya-ku, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Loopback circuit for low-power memory devices
- Patent number 12,243,617
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and techniques for timing mismatch reduction
- Patent number 12,021,531
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Yoshihito Morishita
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device performing loop-back test operation
- Patent number 11,830,565
- Issue date Nov 28, 2023
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses, systems, and methods for system on chip replacement mode
- Patent number 11,651,815
- Issue date May 16, 2023
- Micron Technology, Inc.
- Katsuhiro Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses, systems, and methods for fuse array based device ident...
- Patent number 11,545,210
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device performing loop-back test operation
- Patent number 11,348,660
- Issue date May 31, 2022
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses, systems, and methods for system on chip replacement mode
- Patent number 11,270,758
- Issue date Mar 8, 2022
- Micron Technology, Inc.
- Katsuhiro Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses, systems, and methods for fuse array based device ident...
- Patent number 11,152,052
- Issue date Oct 19, 2021
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOOPBACK CIRCUIT FOR LOW-POWER MEMORY DEVICES
- Publication number 20240144984
- Publication date May 2, 2024
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION
- Publication number 20240072774
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Yoshihito Morishita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE PERFORMING LOOP-BACK TEST OPERATION
- Publication number 20220262451
- Publication date Aug 18, 2022
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE PERFORMING LOOP-BACK TEST OPERATION
- Publication number 20220165350
- Publication date May 26, 2022
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR SYSTEM ON CHIP REPLACEMENT MODE
- Publication number 20220157367
- Publication date May 19, 2022
- Micron Technology, Inc.
- Katsuhiro Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR SYSTEM ON CHIP REPLACEMENT MODE
- Publication number 20220036939
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Katsuhiro Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR FUSE ARRAY BASED DEVICE IDENT...
- Publication number 20210390999
- Publication date Dec 16, 2021
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE

Yoshihito Morishita

Person

Patents Grantslast 30 patents

Loopback circuit for low-power memory devices

Systems and techniques for timing mismatch reduction

Semiconductor device performing loop-back test operation

Apparatuses, systems, and methods for system on chip replacement mode

Apparatuses, systems, and methods for fuse array based device ident...

Semiconductor device performing loop-back test operation

Apparatuses, systems, and methods for system on chip replacement mode

Apparatuses, systems, and methods for fuse array based device ident...

Patents Applicationslast 30 patents

LOOPBACK CIRCUIT FOR LOW-POWER MEMORY DEVICES

SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION

SEMICONDUCTOR DEVICE PERFORMING LOOP-BACK TEST OPERATION

SEMICONDUCTOR DEVICE PERFORMING LOOP-BACK TEST OPERATION

APPARATUSES, SYSTEMS, AND METHODS FOR SYSTEM ON CHIP REPLACEMENT MODE

APPARATUSES, SYSTEMS, AND METHODS FOR SYSTEM ON CHIP REPLACEMENT MODE

APPARATUSES, SYSTEMS, AND METHODS FOR FUSE ARRAY BASED DEVICE IDENT...