Yoshio Inoue

Person

Itami, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method of order fulfilling by making storage units available from a...
- Patent number 11,465,849
- Issue date Oct 11, 2022
- Dematic GmbH
- Shin Yamashita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining power domain by clustering logical blocks based on activa...
- Patent number 8,621,415
- Issue date Dec 31, 2013
- Renesas Electronics Corporation
- Kenta Suto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 8,108,809
- Issue date Jan 31, 2012
- Renesas Electronics Corporation
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floor plan evaluating method, floor plan correcting method, program...
- Patent number 7,730,439
- Issue date Jun 1, 2010
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 7,418,688
- Issue date Aug 26, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic floor-planning method capable of shortening floor-plan pr...
- Patent number 7,017,134
- Issue date Mar 21, 2006
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic placement and routing apparatus automatically inserting a...
- Patent number 6,978,431
- Issue date Dec 20, 2005
- Renesas Technology Corp.
- Koji Hirakimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floorplanning apparatus deciding floor plan using logic seeds assoc...
- Patent number 6,938,232
- Issue date Aug 30, 2005
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Home electronics system enabling display of state of controlled dev...
- Patent number 6,844,807
- Issue date Jan 18, 2005
- Renesas Technology Corp.
- Yoshio Inoue
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for optimizing placement and routing and recor...
- Patent number 6,704,916
- Issue date Mar 9, 2004
- Mitsubishi Denki Kabushiki Kaisha
- Takeshi Nishida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test apparatus
- Patent number 6,691,271
- Issue date Feb 10, 2004
- Mitsubishi Denki Kabushiki Kaisha
- Yusuke Kanehira
- G01 - MEASURING TESTING
Information Patent Grant
Method of designing logic circuit, and computer product
- Patent number 6,654,939
- Issue date Nov 25, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Yu Yamamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining an optimum position of block pins, and compu...
- Patent number 6,606,730
- Issue date Aug 12, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Kiyotake Yoshimaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Receiver for remote control and remote control system having plural...
- Patent number 6,525,669
- Issue date Feb 25, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Shinichiro Ohashi
- G08 - SIGNALLING
Information Patent Grant
Logic circuit verification apparatus and method for semiconductor i...
- Patent number 6,170,072
- Issue date Jan 2, 2001
- Mitsubishi Denki Kabushiki Kaisha
- Yasuo Moriguchi
- G01 - MEASURING TESTING
Information Patent Grant
Logic circuit verification device for semiconductor integrated circuit
- Patent number 6,088,821
- Issue date Jul 11, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Yasuo Moriguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit simulation apparatus having cycle-based simulator for...
- Patent number 6,075,936
- Issue date Jun 13, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Hiroyuki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master slice LSI with integrated fault detection circuitry
- Patent number 5,729,126
- Issue date Mar 17, 1998
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic circuit synthesizer
- Patent number 5,452,230
- Issue date Sep 19, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hiroyuki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices using potential wells or resistive elements a...
- Patent number 5,418,385
- Issue date May 23, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hiroyuki Kawamoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulator for conducting timing analysis of a circuit
- Patent number 5,400,270
- Issue date Mar 21, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Yoshiaki Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device with fault detecting function
- Patent number 5,396,500
- Issue date Mar 7, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Yoshihiro Tanaka
- G01 - MEASURING TESTING
Information Patent Grant
Developing apparatus
- Patent number 5,270,483
- Issue date Dec 14, 1993
- Fuji Xerox Co., Ltd.
- Yoshio Inoue
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Toner cartridge
- Patent number 4,834,246
- Issue date May 30, 1989
- Fuji Xerox Co., Ltd.
- Yoshio Inoue
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Toner concentration detecting device for dry type electrographic co...
- Patent number 4,684,236
- Issue date Aug 4, 1987
- Fuji Xerox Co., Ltd.
- Yoshio Inoue
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
MANAGEMENT DEVICE, MANAGEMENT SYSTEM, METHOD, AND RECORDING MEDIUM
- Publication number 20240153317
- Publication date May 9, 2024
- NEC Corporation
- Yoshio INOUE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF ORDER FULFILLING BY MAKING STORAGE UNITS AVAILABLE FROM A...
- Publication number 20200385211
- Publication date Dec 10, 2020
- Dematic GmbH
- Shin Yamashita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR
- Publication number 20120216166
- Publication date Aug 23, 2012
- Renesas Electronics Corporation
- Kenta SUTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DESIGNING APPARATUS
- Publication number 20120005641
- Publication date Jan 5, 2012
- Renesas Electronics Corporation
- Masanori KURIMOTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floor plan evaluating method, floor plan correcting method, program...
- Publication number 20090024970
- Publication date Jan 22, 2009
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20080295055
- Publication date Nov 27, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20050246676
- Publication date Nov 3, 2005
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic floor-planning method capable of shortening floor-plan pr...
- Publication number 20040228167
- Publication date Nov 18, 2004
- Renesas Technology Corp.
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic placement and routing apparatus automatically inserting a...
- Publication number 20040031007
- Publication date Feb 12, 2004
- Mitsubishi Denki Kabushiki Kaisha
- Koji Hirakimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network terminal haivng a configuration for assigning a network add...
- Publication number 20040001007
- Publication date Jan 1, 2004
- Mitsubishi Denki Kabushiki Kaisha
- Yoshio Inoue
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Floorplanning apparatus deciding floor plan using logic seeds assoc...
- Publication number 20030229874
- Publication date Dec 11, 2003
- Ken Saito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer system provided in a home for inventory management, and in...
- Publication number 20030023493
- Publication date Jan 30, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Shinichiro Ohashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of designing logic circuit, and computer product
- Publication number 20020199161
- Publication date Dec 26, 2002
- Mitsubishi Denki Kabushiki Kaisha
- Yu Yamamoto
- G01 - MEASURING TESTING
Information Patent Application
Home electronics system enabling display of state of controlled dev...
- Publication number 20010030597
- Publication date Oct 18, 2001
- MITSUBUSHI DENKI KABUSHIKI KAISHA
- Yoshio Inoue
- G05 - CONTROLLING REGULATING

Yoshio Inoue

Person

Patents Grantslast 30 patents

Method of order fulfilling by making storage units available from a...

Obtaining power domain by clustering logical blocks based on activa...

Routing analysis method, logic synthesis method and circuit partiti...

Floor plan evaluating method, floor plan correcting method, program...

Routing analysis method, logic synthesis method and circuit partiti...

Automatic floor-planning method capable of shortening floor-plan pr...

Automatic placement and routing apparatus automatically inserting a...

Floorplanning apparatus deciding floor plan using logic seeds assoc...

Home electronics system enabling display of state of controlled dev...

Method and apparatus for optimizing placement and routing and recor...

Built-in self-test apparatus

Method of designing logic circuit, and computer product

Method for determining an optimum position of block pins, and compu...

Receiver for remote control and remote control system having plural...

Logic circuit verification apparatus and method for semiconductor i...

Logic circuit verification device for semiconductor integrated circuit

Logic circuit simulation apparatus having cycle-based simulator for...

Master slice LSI with integrated fault detection circuitry

Logic circuit synthesizer

Semiconductor devices using potential wells or resistive elements a...

Simulator for conducting timing analysis of a circuit

Semiconductor integrated circuit device with fault detecting function

Developing apparatus

Toner cartridge

Toner concentration detecting device for dry type electrographic co...

Patents Applicationslast 30 patents

MANAGEMENT DEVICE, MANAGEMENT SYSTEM, METHOD, AND RECORDING MEDIUM

METHOD OF ORDER FULFILLING BY MAKING STORAGE UNITS AVAILABLE FROM A...

LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM THEREFOR

SEMICONDUCTOR DESIGNING APPARATUS

Floor plan evaluating method, floor plan correcting method, program...

Routing analysis method, logic synthesis method and circuit partiti...

Routing analysis method, logic synthesis method and circuit partiti...

Automatic floor-planning method capable of shortening floor-plan pr...

Automatic placement and routing apparatus automatically inserting a...

Network terminal haivng a configuration for assigning a network add...

Floorplanning apparatus deciding floor plan using logic seeds assoc...

Computer system provided in a home for inventory management, and in...

Method of designing logic circuit, and computer product

Home electronics system enabling display of state of controlled dev...