Yoshitaka Yamauchi

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Bit selection for power reduction in stacking structure during memo...
- Patent number 12,087,378
- Issue date Sep 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Bias generating devices and methods for generating bias
- Patent number 11,953,927
- Issue date Apr 9, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Perng-Fei Yuh
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory devices, semiconductor devices, and methods of operating a m...
- Patent number 11,903,188
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Perng-Fei Yuh
- G11 - INFORMATION STORAGE
Information Patent Grant
Second word line combined with Y-MUX signal in high voltage memory...
- Patent number 11,763,875
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yoshitaka Yamauchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit selection for power reduction in stacking structure during memo...
- Patent number 11,664,081
- Issue date May 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Bit Selection for Power Reduction in Stacking Structure During Memo...
- Publication number 20240386979
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Application
BIAS GENERATING DEVICES AND METHODS FOR GENERATING BIAS
- Publication number 20240210983
- Publication date Jun 27, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- PERNG-FEI YUH
- G05 - CONTROLLING REGULATING
Information Patent Application
MEMORY DEVICES, SEMICONDUCTOR DEVICES, AND METHODS OF OPERATIONS A...
- Publication number 20240147711
- Publication date May 2, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- PERNG-FEI YUH
- G11 - INFORMATION STORAGE
Information Patent Application
SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY...
- Publication number 20230377629
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yoshitaka Yamauchi
- G11 - INFORMATION STORAGE
Information Patent Application
Bit Selection for Power Reduction in Stacking Structure During Memo...
- Publication number 20230282297
- Publication date Sep 7, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES, SEMICONDUCTOR DEVICES, AND METHODS OF OPERATING A...
- Publication number 20230262969
- Publication date Aug 17, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- PERNG-FEI YUH
- G11 - INFORMATION STORAGE
Information Patent Application
SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY...
- Publication number 20220383934
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yoshitaka Yamauchi
- G11 - INFORMATION STORAGE
Information Patent Application
BIAS GENERATING DEVICES AND METHODS FOR GENERATING BIAS
- Publication number 20220342436
- Publication date Oct 27, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- PERNG-FEI YUH
- G05 - CONTROLLING REGULATING
Information Patent Application
Bit Selection for Power Reduction in Stacking Structure During Memo...
- Publication number 20220336031
- Publication date Oct 20, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE

Yoshitaka Yamauchi

Person

Patents Grantslast 30 patents

Bit selection for power reduction in stacking structure during memo...

Bias generating devices and methods for generating bias

Memory devices, semiconductor devices, and methods of operating a m...

Second word line combined with Y-MUX signal in high voltage memory...

Bit selection for power reduction in stacking structure during memo...

Patents Applicationslast 30 patents

Bit Selection for Power Reduction in Stacking Structure During Memo...

BIAS GENERATING DEVICES AND METHODS FOR GENERATING BIAS

MEMORY DEVICES, SEMICONDUCTOR DEVICES, AND METHODS OF OPERATIONS A...

SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY...

Bit Selection for Power Reduction in Stacking Structure During Memo...

MEMORY DEVICES, SEMICONDUCTOR DEVICES, AND METHODS OF OPERATING A...

SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY...

BIAS GENERATING DEVICES AND METHODS FOR GENERATING BIAS

Bit Selection for Power Reduction in Stacking Structure During Memo...