Yoshiyuki Kawakami

Person

Osaka, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor integrated circuit
- Patent number 7,541,625
- Issue date Jun 2, 2009
- Panasonic Corporation
- Yoshiyuki Kawakami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for calculating temporal deterioration margin...
- Patent number 6,795,802
- Issue date Sep 21, 2004
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor integrated circuit and method for designing the same
- Patent number 6,498,515
- Issue date Dec 24, 2002
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit and method for designing the same
- Patent number 6,396,307
- Issue date May 28, 2002
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot carrier effect simulation for integrated circuits
- Patent number 6,278,964
- Issue date Aug 21, 2001
- Matsushita Electric Industrial Co., Ltd.
- Jingkun Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of estimating degradation with consideration of hot carrier...
- Patent number 6,047,247
- Issue date Apr 4, 2000
- Matsushita Electric Industrial Co., Ltd.
- Nobufusa Iwanishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilayer routing method and structure for semiconductor integrate...
- Patent number 5,877,091
- Issue date Mar 2, 1999
- Matsushita Electric Industrial Co. Ltd,
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit and layout designing method for th...
- Patent number 5,774,371
- Issue date Jun 30, 1998
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiring method and system for integrated circuit
- Patent number 5,729,469
- Issue date Mar 17, 1998
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel routing method
- Patent number 5,272,645
- Issue date Dec 21, 1993
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L-shaped channel wiring method
- Patent number 5,241,455
- Issue date Aug 31, 1993
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout pattern generation and geometric processing system for LSI c...
- Patent number 5,062,054
- Issue date Oct 29, 1991
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Integrated Circuit
- Publication number 20080164496
- Publication date Jul 10, 2008
- Yoshiyuki Kawakami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of timing verification and layout optimization
- Publication number 20070143723
- Publication date Jun 21, 2007
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit and method for designing the same
- Publication number 20020140460
- Publication date Oct 3, 2002
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for calculating temporal deterioration margin...
- Publication number 20020022949
- Publication date Feb 21, 2002
- Hirokazu Yonezawa
- G01 - MEASURING TESTING

Yoshiyuki Kawakami

Person

Patents Grantslast 30 patents

Semiconductor integrated circuit

Apparatus and method for calculating temporal deterioration margin...

Semiconductor integrated circuit and method for designing the same

Semiconductor integrated circuit and method for designing the same

Hot carrier effect simulation for integrated circuits

Method of estimating degradation with consideration of hot carrier...

Multilayer routing method and structure for semiconductor integrate...

Semiconductor integrated circuit and layout designing method for th...

Wiring method and system for integrated circuit

Channel routing method

L-shaped channel wiring method

Layout pattern generation and geometric processing system for LSI c...

Patents Applicationslast 30 patents

Semiconductor Integrated Circuit

Method of timing verification and layout optimization

Semiconductor integrated circuit and method for designing the same

Apparatus and method for calculating temporal deterioration margin...