Younsung Choi

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 11,251,093
- Issue date Feb 15, 2022
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 10,734,290
- Issue date Aug 4, 2020
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual pocket approach in PFETs with embedded SI-GE source/drain
- Patent number 10,559,469
- Issue date Feb 11, 2020
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 10,134,643
- Issue date Nov 20, 2018
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded SiGe process for multi-threshold PMOS transistors
- Patent number 10,026,837
- Issue date Jul 17, 2018
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 10,008,499
- Issue date Jun 26, 2018
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,947,765
- Issue date Apr 17, 2018
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 9,812,452
- Issue date Nov 7, 2017
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimized layout for relaxed and strained liner in single stress li...
- Patent number 9,735,159
- Issue date Aug 15, 2017
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 9,583,488
- Issue date Feb 28, 2017
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 9,508,601
- Issue date Nov 29, 2016
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,496,142
- Issue date Nov 15, 2016
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for minimizing transistor and analog component variation in...
- Patent number 8,438,526
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Gregory Charles Baldwin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20200350210
- Publication date Nov 5, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20190057904
- Publication date Feb 21, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS
- Publication number 20180308977
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20180047728
- Publication date Feb 15, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20170133273
- Publication date May 11, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS
- Publication number 20170069755
- Publication date Mar 9, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...
- Publication number 20170062582
- Publication date Mar 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20170047329
- Publication date Feb 16, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH...
- Publication number 20160172443
- Publication date Jun 16, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL POCKET APPROACH IN PFETS WITH EMBEDDED SI-GE SOURCE/DRAIN
- Publication number 20150303061
- Publication date Oct 22, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LI...
- Publication number 20150187772
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASER ANNEALS FOR REDUCED DIODE LEAKAGE
- Publication number 20150187656
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20150187768
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...
- Publication number 20150187585
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20150170972
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN...
- Publication number 20120078604
- Publication date Mar 29, 2012
- Gregory Charles Baldwin
- G06 - COMPUTING CALCULATING COUNTING

Younsung Choi

Person

Patents Grantslast 30 patents

Poly gate extension design methodology to improve CMOS performance...

Poly gate extension design methodology to improve CMOS performance...

Dual pocket approach in PFETs with embedded SI-GE source/drain

Poly gate extension design methodology to improve CMOS performance...

Embedded SiGe process for multi-threshold PMOS transistors

Method to form silicide and contact at embedded epitaxial facet

Dummy gate placement methodology to enhance integrated circuit perf...

Method to form silicide and contact at embedded epitaxial facet

Optimized layout for relaxed and strained liner in single stress li...

Poly gate extension design methodology to improve CMOS performance...

Method to form silicide and contact at embedded epitaxial facet

Dummy gate placement methodology to enhance integrated circuit perf...

Method for minimizing transistor and analog component variation in...

Patents Applicationslast 30 patents

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS

DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH...

DUAL POCKET APPROACH IN PFETS WITH EMBEDDED SI-GE SOURCE/DRAIN

OPTIMIZED LAYOUT FOR RELAXED AND STRAINED LINER IN SINGLE STRESS LI...

LASER ANNEALS FOR REDUCED DIODE LEAKAGE

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERF...

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN...