Yufeng Luo

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Concurrent optimization of 3D-IC with asymmetrical routing layers
- Patent number 11,276,677
- Issue date Mar 15, 2022
- Cadence Design Systems, Inc.
- Liqun Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimization of digital integrated circuit...
- Patent number 7,191,417
- Issue date Mar 13, 2007
- Sierra Design Automation, Inc.
- Yufeng Luo
- G06 - COMPUTING CALCULATING COUNTING