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Yuhei Hayashi
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San Jose, CA, US
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last 30 patents
Information
Patent Grant
Emulation system supporting representation of four-state signals
Patent number
11,900,135
Issue date
Feb 13, 2024
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Architecture and methodology for tuning clock phases to minimize la...
Patent number
11,467,620
Issue date
Oct 11, 2022
Cadence Design Systems, Inc.
Yuhei Hayashi
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Emulation system supporting computation of four-state combinational...
Patent number
11,461,522
Issue date
Oct 4, 2022
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Pseudorandom keephot instructions to mitigate large load steps duri...
Patent number
11,449,337
Issue date
Sep 20, 2022
Cadence Design Systems, Inc.
Mitchell Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Emulation system supporting four-state for sequential logic circuits
Patent number
11,194,942
Issue date
Dec 7, 2021
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Systems and methods for emulation data array compaction
Patent number
11,106,846
Issue date
Aug 31, 2021
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Dynamic netlist modification of compacted data arrays in an emulati...
Patent number
11,048,843
Issue date
Jun 29, 2021
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Functional built-in self-test architecture in an emulation system
Patent number
10,990,728
Issue date
Apr 27, 2021
Cadence Design Systems, Inc.
Mitchell Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Data routing and multiplexing architecture to support serial links...
Patent number
10,860,763
Issue date
Dec 8, 2020
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system to mitigate large power load steps due to intermi...
Patent number
10,386,909
Issue date
Aug 20, 2019
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Enhanced control system for flexible programmable logic and synchro...
Patent number
10,324,740
Issue date
Jun 18, 2019
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system to mitigate large power load steps due to intermi...
Patent number
10,303,230
Issue date
May 28, 2019
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Multiphase I/O for processor-based emulation system
Patent number
9,910,810
Issue date
Mar 6, 2018
Cadence Design Systems, Inc.
Mitchell G. Poplack
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Multiprocessing subsystem with FIFO/buffer modes for flexible input...
Patent number
9,721,048
Issue date
Aug 1, 2017
Cadence Design Systems, Inc.
Mitchell Grant Poplack
G06 - COMPUTING CALCULATING COUNTING