Yuki Ebihara

Person

Chofu, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device with first-in-first-out circuit
- Patent number 11,805,638
- Issue date Oct 31, 2023
- Seiji Narui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with first-in-first-out circuit
- Patent number 10,964,702
- Issue date Mar 30, 2021
- Micron Technology, Inc.
- Seiji Narui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor layered device with data bus inversion
- Patent number 10,922,262
- Issue date Feb 16, 2021
- Micron Technology, Inc.
- Yuki Ebihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared error detection and correction memory
- Patent number 10,854,310
- Issue date Dec 1, 2020
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor layered device with data bus inversion
- Patent number 10,664,432
- Issue date May 26, 2020
- Micron Technology, Inc.
- Yuki Ebihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor layered device with data bus inversion
- Patent number 10,614,024
- Issue date Apr 7, 2020
- Micron Technology, Inc.
- Yuki Ebihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared error detection and correction memory
- Patent number 10,468,114
- Issue date Nov 5, 2019
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared error detection and correction memory
- Patent number 10,008,287
- Issue date Jun 26, 2018
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT
- Publication number 20210225848
- Publication date Jul 22, 2021
- Micron Technology, Inc.
- Seiji Narui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS INVERSION
- Publication number 20200233828
- Publication date Jul 23, 2020
- Micron Technology, Inc.
- Yuki Ebihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT
- Publication number 20200126993
- Publication date Apr 23, 2020
- Micron Technology, Inc.
- Seiji Narui
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS INVERSION
- Publication number 20190361835
- Publication date Nov 28, 2019
- Micron Technology, Inc.
- Yuki Ebihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED ERROR DETECTION AND CORRECTION MEMORY
- Publication number 20190295679
- Publication date Sep 26, 2019
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED ERROR DETECTION AND CORRECTION MEMORY
- Publication number 20180301202
- Publication date Oct 18, 2018
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED ERROR DETECTION AND CORRECTION MEMORY
- Publication number 20180025789
- Publication date Jan 25, 2018
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE

Yuki Ebihara

Person

Patents Grantslast 30 patents

Semiconductor device with first-in-first-out circuit

Semiconductor device with first-in-first-out circuit

Semiconductor layered device with data bus inversion

Shared error detection and correction memory

Semiconductor layered device with data bus inversion

Semiconductor layered device with data bus inversion

Shared error detection and correction memory

Shared error detection and correction memory

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT

SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS INVERSION

SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT

SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS INVERSION

SHARED ERROR DETECTION AND CORRECTION MEMORY

SHARED ERROR DETECTION AND CORRECTION MEMORY

SHARED ERROR DETECTION AND CORRECTION MEMORY