Yukun Lv

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming shallow trenches of the dual active regions
- Patent number 9,871,064
- Issue date Jan 16, 2018
- Shanghai Huali Microelectronics Corporation
- Quan Jing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of etching a shallow trench
- Patent number 9,842,743
- Issue date Dec 12, 2017
- Shanghai Huali Microelectronics Corporation
- Jin Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for establishing mapping relation in STI etch and controllin...
- Patent number 9,666,472
- Issue date May 30, 2017
- Shanghai Huali Microelectronics Corporation
- Jin Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for etching polysilicon gate
- Patent number 8,900,887
- Issue date Dec 2, 2014
- Shanghai Huali Microelectronics Corporation
- Zaifeng Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage bipolar transistor with pseudo buried layers
- Patent number 8,674,480
- Issue date Mar 18, 2014
- Shanghai Hua Hong Nec Electronics Company, Limited
- Tzuyin Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing morphological difference between N-doped and un...
- Patent number 8,658,502
- Issue date Feb 25, 2014
- Shanghai Huali Microelectronics Corporation
- Zaifeng Tang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SIMULATION METHOD OF CMP PROCESS
- Publication number 20180032648
- Publication date Feb 1, 2018
- Yun Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FORMING SHALLOW TRENCHES OF THE DUAL ACTIVE REGIONS
- Publication number 20180033810
- Publication date Feb 1, 2018
- SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Quan Jing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR ESTABLISHING MAPPING RELATION IN STI ETCH AND CONTROLLIN...
- Publication number 20170025304
- Publication date Jan 26, 2017
- Jin Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD INTEGRATING TARGET OPTIMIZATION AND OPTICAL PROXIMITY CORREC...
- Publication number 20160291458
- Publication date Oct 6, 2016
- Daquan He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ETCHING POLYSILICON GATE
- Publication number 20140106475
- Publication date Apr 17, 2014
- SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Zaifeng TANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UN...
- Publication number 20130316539
- Publication date Nov 28, 2013
- SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Zaifeng TANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Voltage Bipolar Transistor with Pseudo Buried Layers
- Publication number 20110140239
- Publication date Jun 16, 2011
- Tzuyin CHIU
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Method for forming shallow trenches of the dual active regions

Method of etching a shallow trench

Method for establishing mapping relation in STI etch and controllin...

Method for etching polysilicon gate

High voltage bipolar transistor with pseudo buried layers

Method for reducing morphological difference between N-doped and un...

Patents Applicationslast 30 patents

SIMULATION METHOD OF CMP PROCESS

METHOD FOR FORMING SHALLOW TRENCHES OF THE DUAL ACTIVE REGIONS

METHOD FOR ESTABLISHING MAPPING RELATION IN STI ETCH AND CONTROLLIN...

METHOD INTEGRATING TARGET OPTIMIZATION AND OPTICAL PROXIMITY CORREC...

METHOD FOR ETCHING POLYSILICON GATE

METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UN...

High Voltage Bipolar Transistor with Pseudo Buried Layers