Yuping REN

Person

Clifton Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gap fill void and connection structures
- Patent number 11,651,992
- Issue date May 16, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Haigou Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gap fill void and connection structures
- Patent number 10,923,388
- Issue date Feb 16, 2021
- GLOBALFOUNDRIES U.S. INC.
- Haigou Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects with non-mandrel cuts formed by early block patterning
- Patent number 10,777,413
- Issue date Sep 15, 2020
- GLOBALFOUNDRIES Inc.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless interconnect vias of semiconductor devices
- Patent number 10,770,344
- Issue date Sep 8, 2020
- GLOBALFOUNDRIES Inc.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation pillar first gate structures and methods of forming same
- Patent number 10,600,914
- Issue date Mar 24, 2020
- GLOBALFOUNDRIES Inc.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mark structure for aligning layers of integrated circuit structure...
- Patent number 10,566,291
- Issue date Feb 18, 2020
- GLOBALFOUNDRIES Inc.
- Ming Hao Tang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Multiple patterning with mandrel cuts formed using a block mask
- Patent number 10,395,926
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Minghao Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects with cuts formed by block patterning
- Patent number 10,319,626
- Issue date Jun 11, 2019
- GLOBALFOUNDRIES Inc.
- Minghao Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selective re-routing of selected areas in a target layer...
- Patent number 10,002,827
- Issue date Jun 19, 2018
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Hard mask etch and dielectric etch aware overlap for via and metal...
- Patent number 9,817,927
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Guo Xiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for selective re-routing of selected areas in a target layer...
- Patent number 9,672,313
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dimension-controlled via formation processing
- Patent number 9,666,476
- Issue date May 30, 2017
- GLOBALFOUNDRIES Inc.
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dimension-controlled via formation processing
- Patent number 9,305,832
- Issue date Apr 5, 2016
- GLOBALFOUNDRIES Inc.
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
GAP FILL VOID AND CONNECTION STRUCTURES
- Publication number 20210134658
- Publication date May 6, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Haigou HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GAP FILL VOID AND CONNECTION STRUCTURES
- Publication number 20200235002
- Publication date Jul 23, 2020
- GLOBALFOUNDRIES INC.
- Haigou HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES
- Publication number 20200219763
- Publication date Jul 9, 2020
- GLOBALFOUNDRIES INC.
- YUPING REN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS WITH NON-MANDREL CUTS FORMED BY EARLY BLOCK PATTERNING
- Publication number 20200020531
- Publication date Jan 16, 2020
- GLOBALFOUNDRIES INC.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MARK STRUCTURE FOR ALIGNING LAYERS OF INTEGRATED CIRCUIT STRUCTURE...
- Publication number 20190259708
- Publication date Aug 22, 2019
- GLOBALFOUNDRIES INC.
- Ming Hao Tang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
ISOLATION PILLAR FIRST GATE STRUCTURES AND METHODS OF FORMING SAME
- Publication number 20190221661
- Publication date Jul 18, 2019
- GLOBALFOUNDRIES INC.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS WITH CUTS FORMED BY BLOCK PATTERNING
- Publication number 20190181040
- Publication date Jun 13, 2019
- GLOBALFOUNDRIES INC.
- Minghao Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...
- Publication number 20170186687
- Publication date Jun 29, 2017
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL...
- Publication number 20170061044
- Publication date Mar 2, 2017
- GLOBALFOUNDRIES INC.
- Guo Xiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...
- Publication number 20160328511
- Publication date Nov 10, 2016
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIMENSION-CONTROLLED VIA FORMATION PROCESSING
- Publication number 20160099171
- Publication date Apr 7, 2016
- GLOBALFOUNDRIES INC.
- Xiang HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIMENSION-CONTROLLED VIA FORMATION PROCESSING
- Publication number 20150380246
- Publication date Dec 31, 2015
- GLOBALFOUNDRIES INC.
- Xiang HU
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Gap fill void and connection structures

Gap fill void and connection structures

Interconnects with non-mandrel cuts formed by early block patterning

Chamferless interconnect vias of semiconductor devices

Isolation pillar first gate structures and methods of forming same

Mark structure for aligning layers of integrated circuit structure...

Multiple patterning with mandrel cuts formed using a block mask

Interconnects with cuts formed by block patterning

Method for selective re-routing of selected areas in a target layer...

Hard mask etch and dielectric etch aware overlap for via and metal...

Method for selective re-routing of selected areas in a target layer...

Dimension-controlled via formation processing

Dimension-controlled via formation processing

Patents Applicationslast 30 patents

GAP FILL VOID AND CONNECTION STRUCTURES

GAP FILL VOID AND CONNECTION STRUCTURES

CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES

INTERCONNECTS WITH NON-MANDREL CUTS FORMED BY EARLY BLOCK PATTERNING

MARK STRUCTURE FOR ALIGNING LAYERS OF INTEGRATED CIRCUIT STRUCTURE...

ISOLATION PILLAR FIRST GATE STRUCTURES AND METHODS OF FORMING SAME

INTERCONNECTS WITH CUTS FORMED BY BLOCK PATTERNING

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...

HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL...

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...

DIMENSION-CONTROLLED VIA FORMATION PROCESSING

DIMENSION-CONTROLLED VIA FORMATION PROCESSING