Yurii S. Shutkin

Person

Moscow, RU

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for encoding and decoding LDPC codes
- Patent number 11,265,014
- Issue date Mar 1, 2022
- Huawei Technologies Co., Ltd.
- Yurii Sergeevich Shutkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficiently decodable QC-LDPC code
- Patent number 11,095,317
- Issue date Aug 17, 2021
- Huawei Technologies Co., Ltd.
- Pavel Anatolyevich Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for encoding and decoding LDPC codes
- Patent number 10,567,002
- Issue date Feb 18, 2020
- Huawei Technologies Co., Ltd.
- Yurii Sergeevich Shutkin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for processing signals carrying modulation-encoded parity...
- Patent number 9,337,866
- Issue date May 10, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Elyar Eldarovich Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel decoder for multiple wireless standards
- Patent number 9,319,181
- Issue date Apr 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimization of data processors with irregular patterns
- Patent number 8,923,413
- Issue date Dec 30, 2014
- LSI Corporation
- Yurii S. Shutkin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
No-delay microsequencer
- Patent number 8,868,890
- Issue date Oct 21, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-pass linear complexity task scheduler
- Patent number 8,850,437
- Issue date Sep 30, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L-value generation in a decoder
- Patent number 8,842,784
- Issue date Sep 23, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Andrey P. Sokolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable parity encoder
- Patent number 8,775,893
- Issue date Jul 8, 2014
- LSI Corporation
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Radix-4 viterbi forward error correction decoding
- Patent number 8,775,914
- Issue date Jul 8, 2014
- LSI Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable encoding per multiple communications standards
- Patent number 8,700,969
- Issue date Apr 15, 2014
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Branch metrics calculation for multiple communications standards
- Patent number 8,699,396
- Issue date Apr 15, 2014
- LSI Corporation
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timer manager architecture based on binary heap
- Patent number 8,656,206
- Issue date Feb 18, 2014
- LSI Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable BCH decoder
- Patent number 8,621,329
- Issue date Dec 31, 2013
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR ENCODING AND DECODING LDPC CODES
- Publication number 20200162107
- Publication date May 21, 2020
- Huawei Technologies Co., Ltd
- Yurii Sergeevich SHUTKIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENTLY DECODABLE QC-LDPC CODE
- Publication number 20190334559
- Publication date Oct 31, 2019
- Huawei Technologies Co., Ltd
- Pavel Anatolyevich PANTELEEV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR ENCODING AND DECODING LDPC CODES
- Publication number 20190260390
- Publication date Aug 22, 2019
- Huawei Technologies Co., Ltd
- Yurii Sergeevich SHUTKIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS FOR PROCESSING SIGNALS CARRYING MODULATION-ENCODED PARITY...
- Publication number 20140359394
- Publication date Dec 4, 2014
- LSI Corporation
- Elyar Eldarovich Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
- Publication number 20140223267
- Publication date Aug 7, 2014
- LSI Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULATION CODING OF PARITY BITS GENERATED USING AN ERROR-CORRECTIO...
- Publication number 20140164876
- Publication date Jun 12, 2014
- Elyar Eldarovich Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED ADD-COMPARE-SELECT CIRCUIT
- Publication number 20140040342
- Publication date Feb 6, 2014
- LSI Corporation
- Andrey P. Sokolov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of Data Processors with Irregular Patterns
- Publication number 20130235907
- Publication date Sep 12, 2013
- LSI Corporation
- Yurii S. Shutkin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VARIABLE PARITY ENCODER
- Publication number 20130019139
- Publication date Jan 17, 2013
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER
- Publication number 20120284731
- Publication date Nov 8, 2012
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DECODER FOR MULTIPLE WIRELESS STANDARDS
- Publication number 20120281790
- Publication date Nov 8, 2012
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP
- Publication number 20120278648
- Publication date Nov 1, 2012
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
- Publication number 20120144274
- Publication date Jun 7, 2012
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS
- Publication number 20120137190
- Publication date May 31, 2012
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS
- Publication number 20120134325
- Publication date May 31, 2012
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
L-VALUE GENERATION IN A DECODER
- Publication number 20120128102
- Publication date May 24, 2012
- Andrey P. Sokolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NO-DELAY MICROSEQUENCER
- Publication number 20120117359
- Publication date May 10, 2012
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE BCH DECODER
- Publication number 20120054586
- Publication date Mar 1, 2012
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY

Yurii S. Shutkin

Person

Patents Grantslast 30 patents

Method and apparatus for encoding and decoding LDPC codes

Efficiently decodable QC-LDPC code

Method and apparatus for encoding and decoding LDPC codes

Apparatus for processing signals carrying modulation-encoded parity...

Parallel decoder for multiple wireless standards

Optimization of data processors with irregular patterns

No-delay microsequencer

Two-pass linear complexity task scheduler

L-value generation in a decoder

Variable parity encoder

Radix-4 viterbi forward error correction decoding

Reconfigurable encoding per multiple communications standards

Branch metrics calculation for multiple communications standards

Timer manager architecture based on binary heap

Reconfigurable BCH decoder

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR ENCODING AND DECODING LDPC CODES

EFFICIENTLY DECODABLE QC-LDPC CODE

METHOD AND APPARATUS FOR ENCODING AND DECODING LDPC CODES

APPARATUS FOR PROCESSING SIGNALS CARRYING MODULATION-ENCODED PARITY...

RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING

MODULATION CODING OF PARITY BITS GENERATED USING AN ERROR-CORRECTIO...

HIGH SPEED ADD-COMPARE-SELECT CIRCUIT

Optimization of Data Processors with Irregular Patterns

VARIABLE PARITY ENCODER

TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER

PARALLEL DECODER FOR MULTIPLE WIRELESS STANDARDS

TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP

RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING

RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS

BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS

L-VALUE GENERATION IN A DECODER

NO-DELAY MICROSEQUENCER

RECONFIGURABLE BCH DECODER