Yuval Yosef

Person

Hadera, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 10,664,284
- Issue date May 26, 2020
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 10,255,077
- Issue date Apr 9, 2019
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Migrating tasks between asymmetric computing elements of a multi-co...
- Patent number 10,185,566
- Issue date Jan 22, 2019
- Intel Corporation
- Alon Naveh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing core having shared front end unit
- Patent number 10,140,129
- Issue date Nov 27, 2018
- Intel Corporation
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address collision detection of ordered parallel threads with...
- Patent number 10,101,999
- Issue date Oct 16, 2018
- Intel Corporation
- Enrique De Lucas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,095,521
- Issue date Oct 9, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,089,113
- Issue date Oct 2, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,083,037
- Issue date Sep 25, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing an asymmetric multicore processor system transparently to...
- Patent number 9,720,730
- Issue date Aug 1, 2017
- Intel Corporation
- Boris Ginzburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 9,588,771
- Issue date Mar 7, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address collision detection of ordered parallel threads with...
- Patent number 9,542,193
- Issue date Jan 10, 2017
- Intel Corporation
- Enrique De Lucas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 9,459,874
- Issue date Oct 4, 2016
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 9,417,873
- Issue date Aug 16, 2016
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 9,361,116
- Issue date Jun 7, 2016
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to manage operational parameters for a processor
- Patent number 9,032,223
- Issue date May 12, 2015
- Intel Corporation
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set architecture-based inter-sequencer communications w...
- Patent number 8,914,618
- Issue date Dec 16, 2014
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware software pipelining for hardware accelerators
- Patent number 8,166,320
- Issue date Apr 24, 2012
- Intel Corporation
- Ron Gabor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware software pipelining for hardware accelerators
- Patent number 7,725,745
- Issue date May 25, 2010
- Intel Corporation
- Ron Gabor
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR
- Publication number 20190196838
- Publication date Jun 27, 2019
- Intel Corporation
- OREN BEN-KIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING CORE HAVING SHARED FRONT END UNIT
- Publication number 20190171462
- Publication date Jun 6, 2019
- Intel Corporation
- ILAN PARDO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ADDRESS COLLISION DETECTION OF ORDERED PARALLEL THREADS WITH...
- Publication number 20170147344
- Publication date May 25, 2017
- Intel Corporation
- ENRIQUE DE LUCAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20170017491
- Publication date Jan 19, 2017
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20170017492
- Publication date Jan 19, 2017
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for a Hybrid Latency-Throughput Processor
- Publication number 20160342419
- Publication date Nov 24, 2016
- Intel Corporation
- Ben Oren-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20160246597
- Publication date Aug 25, 2016
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction Set Architecture-Based Inter-Sequencer Communications W...
- Publication number 20150070368
- Publication date Mar 12, 2015
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20140189332
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing Core Having Shared Front End Unit
- Publication number 20140189300
- Publication date Jul 3, 2014
- Name ILAN PARDO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR
- Publication number 20140189317
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Address Collision Detection Of Ordered Parallel Threads With...
- Publication number 20140189712
- Publication date Jul 3, 2014
- Enrique DE LUCAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CO...
- Publication number 20140129808
- Publication date May 8, 2014
- Alon Naveh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO...
- Publication number 20140082630
- Publication date Mar 20, 2014
- Boris Ginzburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS W...
- Publication number 20130205122
- Publication date Aug 8, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3-D CAMERA
- Publication number 20120056988
- Publication date Mar 8, 2012
- David Stanhill
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Power aware software pipelining for hardware accelerators
- Publication number 20100146314
- Publication date Jun 10, 2010
- Ron Gabor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO MANAGE OPERATIONAL PARAMETERS FOR A PROCESSOR
- Publication number 20100064162
- Publication date Mar 11, 2010
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power aware software pipelining for hardware accelerators
- Publication number 20080148076
- Publication date Jun 19, 2008
- Ron Gabor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction set architecture-based inter-sequencer communications w...
- Publication number 20070157211
- Publication date Jul 5, 2007
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Broadcast system
- Publication number 20050259682
- Publication date Nov 24, 2005
- Yuval Yosef
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Yuval Yosef

Person

Patents Grantslast 30 patents

Apparatus and method for a hybrid latency-throughput processor

Apparatus and method for a hybrid latency-throughput processor

Migrating tasks between asymmetric computing elements of a multi-co...

Processing core having shared front end unit

Memory address collision detection of ordered parallel threads with...

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for low-latency invocation of accelerators

Providing an asymmetric multicore processor system transparently to...

Instruction set architecture-based inter-sequencer communications w...

Memory address collision detection of ordered parallel threads with...

Instruction set architecture-based inter-sequencer communications w...

Apparatus and method for a hybrid latency-throughput processor

Apparatus and method for low-latency invocation of accelerators

Techniques to manage operational parameters for a processor

Instruction set architecture-based inter-sequencer communications w...

Power aware software pipelining for hardware accelerators

Power aware software pipelining for hardware accelerators

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR

PROCESSING CORE HAVING SHARED FRONT END UNIT

MEMORY ADDRESS COLLISION DETECTION OF ORDERED PARALLEL THREADS WITH...

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

Apparatus and Method for a Hybrid Latency-Throughput Processor

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

Instruction Set Architecture-Based Inter-Sequencer Communications W...

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

Processing Core Having Shared Front End Unit

APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR

Memory Address Collision Detection Of Ordered Parallel Threads With...

MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CO...

PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO...

INSTRUCTION SET ARCHITECTURE-BASED INTER-SEQUENCER COMMUNICATIONS W...

3-D CAMERA

Power aware software pipelining for hardware accelerators

TECHNIQUES TO MANAGE OPERATIONAL PARAMETERS FOR A PROCESSOR

Power aware software pipelining for hardware accelerators

Instruction set architecture-based inter-sequencer communications w...

Broadcast system