Yves Thomas Laplanche

Person

Crolles, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-bit scan chain with error-bit generator
- Patent number 12,068,745
- Issue date Aug 20, 2024
- ARM Limited
- Anil Kumar Baratam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via coloring methods and systems
- Patent number 11,900,041
- Issue date Feb 13, 2024
- ARM Limited
- Abhilash Velluridathil Thazhathidathil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling the voltage level on the word line to maintain performa...
- Patent number 9,105,315
- Issue date Aug 11, 2015
- ARM Limited
- Betina Hold
- G11 - INFORMATION STORAGE
Information Patent Grant
Analysing timing paths for circuits formed of standard cells
- Patent number 8,924,766
- Issue date Dec 30, 2014
- ARM Limited
- Jean Luc Pelloie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for determining variation in a predetermined p...
- Patent number 8,779,787
- Issue date Jul 15, 2014
- ARM Limited
- Yves Thomas Laplanche
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Current Measurement Architecture
- Publication number 20240329153
- Publication date Oct 3, 2024
- ARM Limited
- Ashwani Kumar Srivastava
- G01 - MEASURING TESTING
Information Patent Application
Register Bank Architecture with Latches
- Publication number 20240249790
- Publication date Jul 25, 2024
- ARM Limited
- Yannis Jallamion-Grive
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Bit Scan Chain with Error-Bit Generator
- Publication number 20230063727
- Publication date Mar 2, 2023
- ARM Limited
- Anil Kumar Baratam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Via Coloring Methods and Systems
- Publication number 20210109999
- Publication date Apr 15, 2021
- ARM Limited
- Abhilash Velluridathil Thazhathidathil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING THE VOLTAGE LEVEL ON THE WORD LINE TO MAINTAIN PERFORMA...
- Publication number 20140022835
- Publication date Jan 23, 2014
- ARM Limited
- Betina HOLD
- G11 - INFORMATION STORAGE
Information Patent Application
ANALYSING TIMING PATHS FOR CIRCUITS FORMED OF STANDARD CELLS
- Publication number 20130227330
- Publication date Aug 29, 2013
- ARM Limited
- Jean Luc PELLOIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR DETERMINING VARIATION IN A PREDETERMINED P...
- Publication number 20130120009
- Publication date May 16, 2013
- ARM Limited
- Yves Thomas LAPLANCHE
- G01 - MEASURING TESTING
Information Patent Application
REDUCING READ DISTURBS AND WRITE FAILS IN A DATA STORAGE CELL
- Publication number 20130114332
- Publication date May 9, 2013
- ARM Limited
- Yves Thomas LAPLANCHE
- G11 - INFORMATION STORAGE

Yves Thomas Laplanche

Person

Patents Grantslast 30 patents

Multi-bit scan chain with error-bit generator

Via coloring methods and systems

Controlling the voltage level on the word line to maintain performa...

Analysing timing paths for circuits formed of standard cells

Apparatus and method for determining variation in a predetermined p...

Patents Applicationslast 30 patents

Current Measurement Architecture

Register Bank Architecture with Latches

Multi-Bit Scan Chain with Error-Bit Generator

Via Coloring Methods and Systems

CONTROLLING THE VOLTAGE LEVEL ON THE WORD LINE TO MAINTAIN PERFORMA...

ANALYSING TIMING PATHS FOR CIRCUITS FORMED OF STANDARD CELLS

APPARATUS AND METHOD FOR DETERMINING VARIATION IN A PREDETERMINED P...

REDUCING READ DISTURBS AND WRITE FAILS IN A DATA STORAGE CELL