Zarir B. Sarkari

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Synthesis shell generation and use in ASIC design
- Patent number 6,345,378
- Issue date Feb 5, 2002
- LSI Logic Corporation
- Christian Joly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for creating and using design shells for integrated circuit...
- Patent number 5,844,818
- Issue date Dec 1, 1998
- LSI Logic Corporation
- Dan Kochpatcharin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switchable pull-ups and pull-downs for IDDQ testing of integrated c...
- Patent number 5,670,890
- Issue date Sep 23, 1997
- LSI Logic Corporation
- Michael Colwell
- G01 - MEASURING TESTING
Information Patent Grant
Timing shell generation through netlist reduction
- Patent number 5,644,498
- Issue date Jul 1, 1997
- LSI Logic Corporation
- Christian Joly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switchable pull-ups and pull-downs for IDDQ testing of integrated c...
- Patent number 5,644,251
- Issue date Jul 1, 1997
- LSI Logic Corporation
- Michael Colwell
- G01 - MEASURING TESTING