ZESHAN A. CHISHTI

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor and method implementing a cacheline demote machine instru...
- Patent number 11,513,957
- Issue date Nov 29, 2022
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multi-level memory early page demotion
- Patent number 10,860,244
- Issue date Dec 8, 2020
- Intel Corporation
- Binh Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware/software co-optimization to improve performance and energy...
- Patent number 10,817,425
- Issue date Oct 27, 2020
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coarse tag replacement
- Patent number 10,621,094
- Issue date Apr 14, 2020
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregated write back in a direct mapped two level memory
- Patent number 10,496,544
- Issue date Dec 3, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to determine a demarcation voltage to...
- Patent number 10,452,312
- Issue date Oct 22, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Near memory miss prediction to reduce memory access latency
- Patent number 10,417,135
- Issue date Sep 17, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for unneeded block prediction in a computing s...
- Patent number 10,261,901
- Issue date Apr 16, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse superline removal
- Patent number 10,241,916
- Issue date Mar 26, 2019
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level system memory with near memory scrubbing based on predi...
- Patent number 10,120,806
- Issue date Nov 6, 2018
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pre-fetching data in a system having a mul...
- Patent number 10,108,549
- Issue date Oct 23, 2018
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for run-time evaluation of multiple prefetchers
- Patent number 10,102,134
- Issue date Oct 16, 2018
- Intel Corporation
- Zeshan A. Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a heterogeneous memory subsystem
- Patent number 9,921,972
- Issue date Mar 20, 2018
- Intel Corporation
- Christopher B. Wilkerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory management
- Patent number 9,921,961
- Issue date Mar 20, 2018
- Intel Corporation
- Christopher B. Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual shared cache mechanism in a processing device
- Patent number 9,792,212
- Issue date Oct 17, 2017
- Intel Corporation
- Yen-Cheng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing shared cache by multi-core processor
- Patent number 9,710,380
- Issue date Jul 18, 2017
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for thread scheduling on reconfigurable processor...
- Patent number 9,703,708
- Issue date Jul 11, 2017
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level memory management
- Patent number 9,583,182
- Issue date Feb 28, 2017
- Intel Corporation
- Christopher B. Wilkerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing a heterogeneous memory subsystem
- Patent number 9,472,248
- Issue date Oct 18, 2016
- Intel Corporation
- Christopher B. Wilkerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to reduce memory cell refreshes for a memory device
- Patent number 9,418,723
- Issue date Aug 16, 2016
- Intel Corporation
- Zeshan A. Chishti
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for managing reconfigurable processor cores
- Patent number 9,417,879
- Issue date Aug 16, 2016
- Intel Corporation
- Christopher B. Wilkerson
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Instruction and logic for run-time evaluation of multiple prefetchers
- Patent number 9,378,021
- Issue date Jun 28, 2016
- Intel Corporation
- Zeshan A. Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraining prefetch requests to a processor socket
- Patent number 9,286,224
- Issue date Mar 15, 2016
- Intel Corporation
- Seth H. Pugsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gating a portion of a cache memory
- Patent number 9,183,144
- Issue date Nov 10, 2015
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gating a portion of a cache memory
- Patent number 9,176,875
- Issue date Nov 3, 2015
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinating power mode switching and refresh operations in a memor...
- Patent number 9,001,608
- Issue date Apr 7, 2015
- Intel Corporation
- Zeshan A. Chishti
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically allocatable memory error mitigation
- Patent number 8,806,285
- Issue date Aug 12, 2014
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for using cache memory in a system that suppor...
- Patent number 8,640,005
- Issue date Jan 28, 2014
- Intel Corporation
- Christopher B. Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for idle-prioritized memory ranks
- Patent number 8,484,418
- Issue date Jul 9, 2013
- Intel Corporation
- Zeshan A. Chishti
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Hardware support for thread scheduling on multi-core processors
- Patent number 8,276,142
- Issue date Sep 25, 2012
- Intel Corporation
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTO-PREDICATION FOR LOOPS WITH DYNAMICALLY VARYING INTERATION COUNTS
- Publication number 20250004775
- Publication date Jan 2, 2025
- Intel Corporation
- Zeshan Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO IMPLEMENT ADAPTIVE BRANCH PREDICTION THROTT...
- Publication number 20250004781
- Publication date Jan 2, 2025
- Intel Corporation
- Zeshan CHISHTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR MEMORY AND I/O EFFICIENT OPERATIONS ON HOMOMORPHIC...
- Publication number 20210119766
- Publication date Apr 22, 2021
- Intel Corporation
- Vikram B. Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...
- Publication number 20210004328
- Publication date Jan 7, 2021
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
- Publication number 20200226066
- Publication date Jul 16, 2020
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EDGE BATCH REORDERING FOR STREAMING GRAPH ANALYTICS
- Publication number 20200226124
- Publication date Jul 16, 2020
- Intel Corporation
- Zeshan Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NVRAM SYSTEM MEMORY WITH MEMORY SIDE CACHE THAT FAVORS WRITTEN TO I...
- Publication number 20200133884
- Publication date Apr 30, 2020
- Intel Corporation
- Zeshan A. CHISHTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG CACHE ADAPTIVE POWER GATING
- Publication number 20190102314
- Publication date Apr 4, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEAR MEMORY MISS PREDICTION TO REDUCE MEMORY ACCESS LATENCY
- Publication number 20190095332
- Publication date Mar 28, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL MEMORY EARLY PAGE DEMOTION
- Publication number 20190042145
- Publication date Feb 7, 2019
- Intel Corporation
- Binh PHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COARSE TAG REPLACEMENT
- Publication number 20190004952
- Publication date Jan 3, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, METHOD AND SYSTEM FOR JUST-IN-TIME CACHE ASSOCIATIVITY
- Publication number 20180285274
- Publication date Oct 4, 2018
- Intel Corporation
- Elvira TERAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE SUPERLINE REMOVAL
- Publication number 20180285271
- Publication date Oct 4, 2018
- Intel Corporation
- Zvika GREENFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER MANAGEMENT SCHEME BASED ON LINK'S PRIOR HISTORY
- Publication number 20180188797
- Publication date Jul 5, 2018
- Intel Corporation
- Zhe WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM AND METHOD TO DETERMINE A DEMARCATION VOLTAGE TO...
- Publication number 20180188953
- Publication date Jul 5, 2018
- Intel Corporation
- Zhe WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATED WRITE BACK IN A DIRECT MAPPED TWO LEVEL MEMORY
- Publication number 20180189182
- Publication date Jul 5, 2018
- Intel Corporation
- Zhe WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Level System Memory With Near Memory Scrubbing Based On Predi...
- Publication number 20170371795
- Publication date Dec 28, 2017
- Intel Corporation
- Zhe WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL MEMORY MANAGEMENT
- Publication number 20170277633
- Publication date Sep 28, 2017
- Intel Corporation
- Christopher B. WILKERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR UNNEEDED BLOCK PREDICTION IN A COMPUTING S...
- Publication number 20170091093
- Publication date Mar 30, 2017
- ZHE WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PRE-FETCHING DATA IN A SYSTEM HAVING A MUL...
- Publication number 20170083443
- Publication date Mar 23, 2017
- ZHE WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Data Compression for Data Storage in a Memory Device
- Publication number 20170046074
- Publication date Feb 16, 2017
- Intel Corporation
- REN WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM
- Publication number 20170017580
- Publication date Jan 19, 2017
- CHRISTOPHER B. WILKERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Run-time Evaluation of Multiple Prefetchers
- Publication number 20160299847
- Publication date Oct 13, 2016
- Intel Corporation
- Zeshan A. Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...
- Publication number 20160188474
- Publication date Jun 30, 2016
- Intel Corporation
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques to Reduce Memory Cell Refreshes for a Memory Device
- Publication number 20160180917
- Publication date Jun 23, 2016
- ZESHAN A. CHISHTI
- G11 - INFORMATION STORAGE
Information Patent Application
Virtual Shared Cache Mechanism in a Processing Device
- Publication number 20160077970
- Publication date Mar 17, 2016
- Intel Corporation
- Yen-Cheng Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM
- Publication number 20150278091
- Publication date Oct 1, 2015
- Intel Corporation
- CHRISTOPHER B. WILKERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Run-time Evaluation of Multiple Prefetchers
- Publication number 20150234663
- Publication date Aug 20, 2015
- Zeshan A. Chishti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET
- Publication number 20150149714
- Publication date May 28, 2015
- Seth H. Pugsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR THREAD SCHEDULING ON RECONFIGURABLE PROCESSOR...
- Publication number 20150095918
- Publication date Apr 2, 2015
- Alaa R. Alameldeen
- G06 - COMPUTING CALCULATING COUNTING

ZESHAN A. CHISHTI

Person

Patents Grantslast 30 patents

Processor and method implementing a cacheline demote machine instru...

Method and apparatus for multi-level memory early page demotion

Hardware/software co-optimization to improve performance and energy...

Coarse tag replacement

Aggregated write back in a direct mapped two level memory

Apparatus, system, and method to determine a demarcation voltage to...

Near memory miss prediction to reduce memory access latency

Method and apparatus for unneeded block prediction in a computing s...

Sparse superline removal

Multi-level system memory with near memory scrubbing based on predi...

Method and apparatus for pre-fetching data in a system having a mul...

Instruction and logic for run-time evaluation of multiple prefetchers

Method and apparatus for implementing a heterogeneous memory subsystem

Multi-level memory management

Virtual shared cache mechanism in a processing device

Managing shared cache by multi-core processor

System and method for thread scheduling on reconfigurable processor...

Multi-level memory management

Method and apparatus for implementing a heterogeneous memory subsystem

Techniques to reduce memory cell refreshes for a memory device

Systems and methods for managing reconfigurable processor cores

Instruction and logic for run-time evaluation of multiple prefetchers

Constraining prefetch requests to a processor socket

Power gating a portion of a cache memory

Power gating a portion of a cache memory

Coordinating power mode switching and refresh operations in a memor...

Dynamically allocatable memory error mitigation

Method and apparatus for using cache memory in a system that suppor...

Methods and apparatuses for idle-prioritized memory ranks

Hardware support for thread scheduling on multi-core processors

Patents Applicationslast 30 patents

AUTO-PREDICATION FOR LOOPS WITH DYNAMICALLY VARYING INTERATION COUNTS

METHOD AND APPARATUS TO IMPLEMENT ADAPTIVE BRANCH PREDICTION THROTT...

TECHNOLOGIES FOR MEMORY AND I/O EFFICIENT OPERATIONS ON HOMOMORPHIC...

HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...

APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY

EDGE BATCH REORDERING FOR STREAMING GRAPH ANALYTICS

NVRAM SYSTEM MEMORY WITH MEMORY SIDE CACHE THAT FAVORS WRITTEN TO I...

TAG CACHE ADAPTIVE POWER GATING

NEAR MEMORY MISS PREDICTION TO REDUCE MEMORY ACCESS LATENCY

METHOD AND APPARATUS FOR MULTI-LEVEL MEMORY EARLY PAGE DEMOTION

COARSE TAG REPLACEMENT

APPARATUS, METHOD AND SYSTEM FOR JUST-IN-TIME CACHE ASSOCIATIVITY

SPARSE SUPERLINE REMOVAL

LINK POWER MANAGEMENT SCHEME BASED ON LINK'S PRIOR HISTORY

APPARATUS, SYSTEM AND METHOD TO DETERMINE A DEMARCATION VOLTAGE TO...

AGGREGATED WRITE BACK IN A DIRECT MAPPED TWO LEVEL MEMORY

Multi-Level System Memory With Near Memory Scrubbing Based On Predi...

MULTI-LEVEL MEMORY MANAGEMENT

METHOD AND APPARATUS FOR UNNEEDED BLOCK PREDICTION IN A COMPUTING S...

METHOD AND APPARATUS FOR PRE-FETCHING DATA IN A SYSTEM HAVING A MUL...

Adaptive Data Compression for Data Storage in a Memory Device

METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM

Instruction and Logic for Run-time Evaluation of Multiple Prefetchers

HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY...

Techniques to Reduce Memory Cell Refreshes for a Memory Device

Virtual Shared Cache Mechanism in a Processing Device

METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM

Instruction and Logic for Run-time Evaluation of Multiple Prefetchers

CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET

SYSTEM AND METHOD FOR THREAD SCHEDULING ON RECONFIGURABLE PROCESSOR...