Zhe-Wei JIANG

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Metal cut optimization for standard cells
- Patent number 12,106,033
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitive isolation structure insert for reversed signals
- Patent number 12,073,162
- Issue date Aug 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout for integrated circuit and the integrated circuit
- Patent number 11,907,633
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout context-based cell timing characterization
- Patent number 11,853,676
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Zhe-Wei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal cut optimization for standard cells
- Patent number 11,734,481
- Issue date Aug 22, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout context-based cell timing characterization
- Patent number 11,531,802
- Issue date Dec 20, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Zhe-Wei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitive isolation structure insert for reversed signals
- Patent number 11,526,649
- Issue date Dec 13, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout for integrated circuit and the integrated circuit
- Patent number 11,494,543
- Issue date Nov 8, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal cut optimization for standard cells
- Patent number 11,030,368
- Issue date Jun 8, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitive isolation structure insert for reversed signals
- Patent number 10,943,050
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal cut optimization for standard cells
- Patent number 10,691,849
- Issue date Jun 23, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout for integrated circuit and the integrated circuit
- Patent number 10,685,162
- Issue date Jun 16, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout method for integrated circuit and layout of the integrated c...
- Patent number 10,163,883
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Company Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of forming layout design
- Patent number 9,626,472
- Issue date Apr 18, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ting-Wei Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of layout placement based on multilayer gridlines
- Patent number 9,536,032
- Issue date Jan 3, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ting-Wei Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for leakage estimation for standard integrated ci...
- Patent number 9,058,462
- Issue date Jun 16, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- King-Ho Tam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming a layout including cells having different thresho...
- Patent number 8,826,212
- Issue date Sep 2, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sung-Yen Yeh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
DFM improvement utility with unified interface
- Patent number 8,726,208
- Issue date May 13, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hao Chen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Cell architecture and method
- Patent number 8,356,262
- Issue date Jan 15, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing system and method for double patterning technology
- Patent number 8,239,806
- Issue date Aug 7, 2012
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Huang-Yu Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS
- Publication number 20240362387
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION
- Publication number 20240095434
- Publication date Mar 21, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- ZHE-WEI JIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL CUT OPTIMIZATION FOR STANDARD CELLS
- Publication number 20230334208
- Publication date Oct 19, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION
- Publication number 20230107940
- Publication date Apr 6, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- ZHE-WEI JIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS
- Publication number 20230090213
- Publication date Mar 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
- Publication number 20220382948
- Publication date Dec 1, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- CHEOK-KEI LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL CUT OPTIMIZATION FOR STANDARD CELLS
- Publication number 20210271794
- Publication date Sep 2, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Transistor Placement in Standard Cell Layout
- Publication number 20210200927
- Publication date Jul 1, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheok-Kei Lei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS
- Publication number 20210192118
- Publication date Jun 24, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION
- Publication number 20210117603
- Publication date Apr 22, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- ZHE-WEI JIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL CUT OPTIMIZATION FOR STANDARD CELLS
- Publication number 20200285792
- Publication date Sep 10, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
- Publication number 20200285797
- Publication date Sep 10, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- CHEOK-KEI LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS
- Publication number 20200134130
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT
- Publication number 20190121931
- Publication date Apr 25, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- CHEOK-KEI LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Metal Cut Optimization for Standard Cells
- Publication number 20190095552
- Publication date Mar 28, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheok-Kei LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT METHOD FOR INTEGRATED CIRCUIT AND LAYOUT OF THE INTEGRATED C...
- Publication number 20170365592
- Publication date Dec 21, 2017
- Taiwan Semiconductor Manufacturing company Ltd.
- CHEOK-KEI LEI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF FORMING LAYOUT DESIGN
- Publication number 20160147927
- Publication date May 26, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ting-Wei CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF FORMING LAYOUT DESIGN
- Publication number 20160147926
- Publication date May 26, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ting-Wei CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CI...
- Publication number 20150067624
- Publication date Mar 5, 2015
- Taiwan Semiconductor Manufacturing company Ltd.
- King-Ho TAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FORMING A LAYOUT INCLUDING CELLS HAVING DIFFERENT THRESHO...
- Publication number 20140165020
- Publication date Jun 12, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sung-Yen YEH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DFM Improvement Utility with Unified Interface
- Publication number 20130024832
- Publication date Jan 24, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hao Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL ARCHITECTURE AND METHOD
- Publication number 20120331426
- Publication date Dec 27, 2012
- Taiwan Semiconductor Manufacturing Co., LTD
- Lee-Chung LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY
- Publication number 20110119648
- Publication date May 19, 2011
- Taiwan Semiconductor Manufacturing Co., LTD
- Huang-Yu Chen
- G06 - COMPUTING CALCULATING COUNTING

Zhe-Wei JIANG

Person

Patents Grantslast 30 patents

Metal cut optimization for standard cells

Capacitive isolation structure insert for reversed signals

Layout for integrated circuit and the integrated circuit

Layout context-based cell timing characterization

Metal cut optimization for standard cells

Layout context-based cell timing characterization

Capacitive isolation structure insert for reversed signals

Layout for integrated circuit and the integrated circuit

Metal cut optimization for standard cells

Capacitive isolation structure insert for reversed signals

Metal cut optimization for standard cells

Layout for integrated circuit and the integrated circuit

Layout method for integrated circuit and layout of the integrated c...

Method and system of forming layout design

Method and system of layout placement based on multilayer gridlines

System and method for leakage estimation for standard integrated ci...

Method of forming a layout including cells having different thresho...

DFM improvement utility with unified interface

Cell architecture and method

Routing system and method for double patterning technology

Patents Applicationslast 30 patents

CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

METAL CUT OPTIMIZATION FOR STANDARD CELLS

LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT

METAL CUT OPTIMIZATION FOR STANDARD CELLS

System and Method for Transistor Placement in Standard Cell Layout

CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

LAYOUT CONTEXT-BASED CELL TIMING CHARACTERIZATION

METAL CUT OPTIMIZATION FOR STANDARD CELLS

LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT

CAPACITIVE ISOLATION STRUCTURE INSERT FOR REVERSED SIGNALS

LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT

Metal Cut Optimization for Standard Cells

LAYOUT METHOD FOR INTEGRATED CIRCUIT AND LAYOUT OF THE INTEGRATED C...

METHOD AND SYSTEM OF FORMING LAYOUT DESIGN

METHOD AND SYSTEM OF FORMING LAYOUT DESIGN

SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CI...

METHOD OF FORMING A LAYOUT INCLUDING CELLS HAVING DIFFERENT THRESHO...

DFM Improvement Utility with Unified Interface

CELL ARCHITECTURE AND METHOD

ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY