Zheng Chen

Person

Macungie, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Highly secure and extensive scan testing of integrated circuits
- Patent number 8,977,917
- Issue date Mar 10, 2015
- Lattice Semiconductor Corporation
- Wei Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable response mode for synchronous data read
- Patent number 8,816,718
- Issue date Aug 26, 2014
- Lattice Semiconductor Corporation
- Wei Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Blocking memory readback in a programmable logic device
- Patent number 8,522,126
- Issue date Aug 27, 2013
- Lattice Semiconductor Corporation
- Zheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Triggered sense amplifier
- Patent number 8,477,549
- Issue date Jul 2, 2013
- Lattice Semiconductor Corporation
- Rohith Sood
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power configurable delay element
- Patent number 8,461,894
- Issue date Jun 11, 2013
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pre-configuration programmability of I/O circuitry
- Patent number 8,384,428
- Issue date Feb 26, 2013
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device wakeup using a general purpose input/outp...
- Patent number 8,368,424
- Issue date Feb 5, 2013
- Lattice Semiconductor Corporation
- Wei Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitline floating circuit for memory power reduction
- Patent number 8,351,287
- Issue date Jan 8, 2013
- Lattice Semiconductor Corporation
- Rohith Sood
- G11 - INFORMATION STORAGE
Information Patent Grant
Safe programming of key information into non-volatile memory for a...
- Patent number 8,319,521
- Issue date Nov 27, 2012
- Lattice Semiconductor Corporation
- Wei Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power, glitch-less, configurable delay element
- Patent number 8,248,136
- Issue date Aug 21, 2012
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple communication channel configuration systems and methods
- Patent number 7,831,754
- Issue date Nov 9, 2010
- Lattice Semiconductor Corporation
- Zheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient bitstream compression
- Patent number 7,808,405
- Issue date Oct 5, 2010
- Lattice Semiconductor Corporation
- Zheng Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Jitter tolerant delay-locked loop circuit
- Patent number 7,620,839
- Issue date Nov 17, 2009
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-and-data-recovery system having a multi-phase clock generator...
- Patent number 7,599,457
- Issue date Oct 6, 2009
- Lattice Semiconductor Corporation
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic delay or advance adjustment of oscillating signal phase
- Patent number 7,586,344
- Issue date Sep 8, 2009
- Lattice Semiconductor Corporation
- Richard Booth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient configuration of daisy-chained programmable logic devices
- Patent number 7,554,357
- Issue date Jun 30, 2009
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient bitstream compression
- Patent number 7,511,641
- Issue date Mar 31, 2009
- Lattice Semiconductor Corporation
- Zheng Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Initializing memory blocks
- Patent number 7,177,221
- Issue date Feb 13, 2007
- Lattice Semiconductor Corporation
- Zheng Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power asynchronous sense amp
- Patent number 7,161,862
- Issue date Jan 9, 2007
- Lattice Semiconductor Corporation
- Mou C. Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Digitally controlled delay cells
- Patent number 7,009,433
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,975,137
- Issue date Dec 13, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable broadcast initialization of memory blocks
- Patent number 6,940,779
- Issue date Sep 6, 2005
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory access via serial memory interface
- Patent number 6,903,574
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Bi-directional buffering for memory data lines
- Patent number 6,882,555
- Issue date Apr 19, 2005
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,870,395
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array (FPGA) bit stream format
- Patent number 6,772,230
- Issue date Aug 3, 2004
- Lattice Semiconductor Corp.
- Zheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-master multi-slave system bus in a field programmable gate ar...
- Patent number 6,483,342
- Issue date Nov 19, 2002
- Lattice Semiconductor Corporation
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGHLY SECURE AND EXTENSIVE SCAN TESTING OF INTEGRATED CIRCUITS
- Publication number 20140136914
- Publication date May 15, 2014
- Lattice Semiconductor Corporation
- Wei Han
- G01 - MEASURING TESTING
Information Patent Application
Efficient configuration of daisy-chained programmable logic devices
- Publication number 20070182445
- Publication date Aug 9, 2007
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Jitter tolerant delay-locked loop circuit
- Publication number 20070136619
- Publication date Jun 14, 2007
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock-and-data-recovery system having a multi-phase clock generator...
- Publication number 20070030936
- Publication date Feb 8, 2007
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multiplexer circuits
- Publication number 20050093577
- Publication date May 5, 2005
- Liem Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable broadcast initialization of memory blocks
- Publication number 20050035781
- Publication date Feb 17, 2005
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory access via serial memory interface
- Publication number 20050024085
- Publication date Feb 3, 2005
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Bi-directional buffering for memory data lines
- Publication number 20040257860
- Publication date Dec 23, 2004
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Application
Digitally controlled delay cells
- Publication number 20040239387
- Publication date Dec 2, 2004
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices with integrated standard-cell logic blocks
- Publication number 20040183564
- Publication date Sep 23, 2004
- Lattice Semiconductor Corporation, a Delaware corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-master multi-slave system bus in a field programmable gate ar...
- Publication number 20020008540
- Publication date Jan 24, 2002
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Field programmable gate array (FPGA) bit stream cormat
- Publication number 20020010902
- Publication date Jan 24, 2002
- Zheng Chen
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Highly secure and extensive scan testing of integrated circuits

Variable response mode for synchronous data read

Blocking memory readback in a programmable logic device

Triggered sense amplifier

Low-power configurable delay element

Pre-configuration programmability of I/O circuitry

Programmable logic device wakeup using a general purpose input/outp...

Bitline floating circuit for memory power reduction

Safe programming of key information into non-volatile memory for a...

Low-power, glitch-less, configurable delay element

Multiple communication channel configuration systems and methods

Efficient bitstream compression

Jitter tolerant delay-locked loop circuit

Clock-and-data-recovery system having a multi-phase clock generator...

Dynamic delay or advance adjustment of oscillating signal phase

Efficient configuration of daisy-chained programmable logic devices

Efficient bitstream compression

Initializing memory blocks

Low power asynchronous sense amp

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Programmable broadcast initialization of memory blocks

Memory access via serial memory interface

Bi-directional buffering for memory data lines

Programmable logic devices with integrated standard-cell logic blocks

Field programmable gate array (FPGA) bit stream format

Multi-master multi-slave system bus in a field programmable gate ar...

Patents Applicationslast 30 patents

HIGHLY SECURE AND EXTENSIVE SCAN TESTING OF INTEGRATED CIRCUITS

Efficient configuration of daisy-chained programmable logic devices

Jitter tolerant delay-locked loop circuit

Clock-and-data-recovery system having a multi-phase clock generator...

Multiplexer circuits

Programmable broadcast initialization of memory blocks

Memory access via serial memory interface

Bi-directional buffering for memory data lines

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Multi-master multi-slave system bus in a field programmable gate ar...

Field programmable gate array (FPGA) bit stream cormat