Zheng Wei

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flash memory cells having trenched storage elements
- Patent number 9,917,211
- Issue date Mar 13, 2018
- Cypress Semiconductor Corporation
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 9,318,373
- Issue date Apr 19, 2016
- Cypress Semiconductor Corporation
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating memory cells having split charge storage nodes
- Patent number 9,159,568
- Issue date Oct 13, 2015
- Cypress Semiconductor Corporation
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory system with Fin FET technology
- Patent number 8,785,268
- Issue date Jul 22, 2014
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cells having trenched storage elements
- Patent number 8,742,486
- Issue date Jun 3, 2014
- Spansion, LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices containing a high-K dielectric layer
- Patent number 8,691,647
- Issue date Apr 8, 2014
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 8,445,966
- Issue date May 21, 2013
- Spansion LLC
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Strapping contact for charge protection
- Patent number 8,404,541
- Issue date Mar 26, 2013
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Erasing flash memory using adaptive drain and/or gate bias
- Patent number 8,144,522
- Issue date Mar 27, 2012
- Spansion LLC
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 8,076,712
- Issue date Dec 13, 2011
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,952,938
- Issue date May 31, 2011
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-bit memory device having trench isolation material disposed ne...
- Patent number 7,948,052
- Issue date May 24, 2011
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating dual bit flash memory devices
- Patent number 7,867,848
- Issue date Jan 11, 2011
- Spansion, LLC
- Minghao Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory device with improved erase speed
- Patent number 7,863,128
- Issue date Jan 4, 2011
- Spansion LLC
- Joong Jeon
- G11 - INFORMATION STORAGE
Information Patent Grant
High K stack for non-volatile memory
- Patent number 7,855,114
- Issue date Dec 21, 2010
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Erasing flash memory using adaptive drain and/or gate bias
- Patent number 7,778,088
- Issue date Aug 17, 2010
- Spansion LLC
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 7,767,517
- Issue date Aug 3, 2010
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strapping contact for charge protection
- Patent number 7,750,407
- Issue date Jul 6, 2010
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming in memory devices using source bitline voltage bias
- Patent number 7,746,698
- Issue date Jun 29, 2010
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,746,705
- Issue date Jun 29, 2010
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating dual bit flash memory devices
- Patent number 7,732,281
- Issue date Jun 8, 2010
- Spansion LLC
- Minghao Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating flash memory devices
- Patent number 7,696,038
- Issue date Apr 13, 2010
- Spansion LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
P-channel NAND in isolated N-well
- Patent number 7,671,403
- Issue date Mar 2, 2010
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a split charge storage node semiconductor m...
- Patent number 7,666,739
- Issue date Feb 23, 2010
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Work function engineering for FN erase of a memory device with mult...
- Patent number 7,659,569
- Issue date Feb 9, 2010
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having implanted oxide to block electron drift, and m...
- Patent number 7,622,373
- Issue date Nov 24, 2009
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back-to-back NPN/PNP protection diodes
- Patent number 7,573,103
- Issue date Aug 11, 2009
- Spansion LLC
- Yi He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High K stack for non-volatile memory
- Patent number 7,492,001
- Issue date Feb 17, 2009
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative wordline bias for reduction of leakage current during flas...
- Patent number 7,463,525
- Issue date Dec 9, 2008
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for protecting semiconductor devices
- Patent number 7,402,868
- Issue date Jul 22, 2008
- Spansion LLC
- Ihsan Jahed Djomehri
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS
- Publication number 20140225177
- Publication date Aug 14, 2014
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20130237022
- Publication date Sep 12, 2013
- SPANSION LLC
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20100283100
- Publication date Nov 11, 2010
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
- Publication number 20100265775
- Publication date Oct 21, 2010
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20100240210
- Publication date Sep 23, 2010
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...
- Publication number 20100208527
- Publication date Aug 19, 2010
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
- Publication number 20100203694
- Publication date Aug 12, 2010
- Minghao SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
- Publication number 20090154246
- Publication date Jun 18, 2009
- SPANSION LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH K STACK FOR NON-VOLATILE MEMORY
- Publication number 20090155992
- Publication date Jun 18, 2009
- SPANSION LLC
- Wei ZHENG
- G11 - INFORMATION STORAGE
Information Patent Application
WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTI...
- Publication number 20090146201
- Publication date Jun 11, 2009
- SPANSION LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
Selective Application Of Word Line Bias To Minimize Fringe Effects...
- Publication number 20090147589
- Publication date Jun 11, 2009
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH DEPLETION GATE
- Publication number 20080150005
- Publication date Jun 26, 2008
- SPANSION LLC
- Meng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY SYSTEM WITH FIN FET TECHNOLOGY
- Publication number 20080150029
- Publication date Jun 26, 2008
- SPANSION LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE HAVING IMPLANTED OXIDE TO BLOCK ELECTRON DRIFT, AND M...
- Publication number 20080150001
- Publication date Jun 26, 2008
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR M...
- Publication number 20080153222
- Publication date Jun 26, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20080149999
- Publication date Jun 26, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20080151590
- Publication date Jun 26, 2008
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE WORDLINE BIAS FOR REDUCTION OF LEAKAGE CURRENT DURING FLAS...
- Publication number 20080151634
- Publication date Jun 26, 2008
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
- Publication number 20080150011
- Publication date Jun 26, 2008
- SPANSION LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-BIT MEMORY DEVICE HAVING TRENCH ISOLATION MATERIAL DISPOSED NE...
- Publication number 20080144366
- Publication date Jun 19, 2008
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
- Publication number 20080144396
- Publication date Jun 19, 2008
- Kuo-Tung Chang
- G11 - INFORMATION STORAGE
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20080142889
- Publication date Jun 19, 2008
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cells having split charge storage nodes and methods for fabr...
- Publication number 20080142875
- Publication date Jun 19, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
P-CHANNEL NAND IN ISOLATED N-WELL
- Publication number 20080135918
- Publication date Jun 12, 2008
- SPANSION LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual charge storage node with undercut gate oxide for deep sub-micr...
- Publication number 20080061359
- Publication date Mar 13, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for erasing and programming memory devices
- Publication number 20070247923
- Publication date Oct 25, 2007
- Meng Ding
- G11 - INFORMATION STORAGE
Information Patent Application
Methods for erasing memory devices and multi-level programming memo...
- Publication number 20070247924
- Publication date Oct 25, 2007
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory cells having trenched storage elements
- Publication number 20070205455
- Publication date Sep 6, 2007
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Split gate multi-bit memory cell
- Publication number 20060226468
- Publication date Oct 12, 2006
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High K stack for non-volatile memory
- Publication number 20060216888
- Publication date Sep 28, 2006
- Wei Zheng
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Flash memory cells having trenched storage elements

Method and apparatus for protection against process-induced charging

Method for fabricating memory cells having split charge storage nodes

Memory system with Fin FET technology

Flash memory cells having trenched storage elements

Memory devices containing a high-K dielectric layer

Method and apparatus for protection against process-induced charging

Strapping contact for charge protection

Erasing flash memory using adaptive drain and/or gate bias

Semiconductor memory comprising dual charge storage nodes and metho...

Selective application of word line bias to minimize fringe effects...

Dual-bit memory device having trench isolation material disposed ne...

Methods for fabricating dual bit flash memory devices

Non-volatile memory device with improved erase speed

High K stack for non-volatile memory

Erasing flash memory using adaptive drain and/or gate bias

Semiconductor memory comprising dual charge storage nodes and metho...

Strapping contact for charge protection

Programming in memory devices using source bitline voltage bias

Selective application of word line bias to minimize fringe effects...

Methods for fabricating dual bit flash memory devices

Methods for fabricating flash memory devices

P-channel NAND in isolated N-well

Methods for fabricating a split charge storage node semiconductor m...

Work function engineering for FN erase of a memory device with mult...

Memory device having implanted oxide to block electron drift, and m...

Back-to-back NPN/PNP protection diodes

High K stack for non-volatile memory

Negative wordline bias for reduction of leakage current during flas...

System and method for protecting semiconductor devices

Patents Applicationslast 30 patents

FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS

STRAPPING CONTACT FOR CHARGE PROTECTION

SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...

METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES

PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS

HIGH K STACK FOR NON-VOLATILE MEMORY

WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTI...

Selective Application Of Word Line Bias To Minimize Fringe Effects...

MEMORY SYSTEM WITH DEPLETION GATE

MEMORY SYSTEM WITH FIN FET TECHNOLOGY

MEMORY DEVICE HAVING IMPLANTED OXIDE TO BLOCK ELECTRON DRIFT, AND M...

METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR M...

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

NEGATIVE WORDLINE BIAS FOR REDUCTION OF LEAKAGE CURRENT DURING FLAS...

INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM

DUAL-BIT MEMORY DEVICE HAVING TRENCH ISOLATION MATERIAL DISPOSED NE...

ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS

STRAPPING CONTACT FOR CHARGE PROTECTION

Memory cells having split charge storage nodes and methods for fabr...

P-CHANNEL NAND IN ISOLATED N-WELL

Dual charge storage node with undercut gate oxide for deep sub-micr...

Methods for erasing and programming memory devices

Methods for erasing memory devices and multi-level programming memo...

Flash memory cells having trenched storage elements

Split gate multi-bit memory cell

High K stack for non-volatile memory