Zhicheng DING

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Film in substrate for releasing z stack-up constraint
- Patent number 12,027,496
- Issue date Jul 2, 2024
- Intel Corporation
- Jianfeng Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Joint connection of corner non-critical to function (NCTF) ball for...
- Patent number 11,990,395
- Issue date May 21, 2024
- Intel Corporation
- Xiaoying Tang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power enhanced stacked chip scale package solution with integrated...
- Patent number 11,894,344
- Issue date Feb 6, 2024
- Intel Corporation
- Zhijun Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die stack with reduced warpage
- Patent number 11,848,281
- Issue date Dec 19, 2023
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device package
- Patent number 11,830,848
- Issue date Nov 28, 2023
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure fabricated using lithographic and deposition...
- Patent number 11,742,284
- Issue date Aug 29, 2023
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical bond-wire stacked chip-scale package with application-spec...
- Patent number 11,538,746
- Issue date Dec 27, 2022
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power enhanced stacked chip scale package solution with integrated...
- Patent number 11,302,671
- Issue date Apr 12, 2022
- Intel Corporation
- Zhijun Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Input device for intelligent terminal
- Patent number 11,148,044
- Issue date Oct 19, 2021
- SHANGHAI ZHONGLIAN TECHNOLOGIES LTD., CO
- Haitao Duan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip-chip like integrated passive prepackage for SIP device
- Patent number 11,101,254
- Issue date Aug 24, 2021
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die stack with reduced warpage
- Patent number 11,081,451
- Issue date Aug 3, 2021
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stair-stacked dice device in a system in package, and methods of ma...
- Patent number 10,991,679
- Issue date Apr 27, 2021
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prepackaged stair-stacked memory module in a chip scale system in p...
- Patent number 10,930,622
- Issue date Feb 23, 2021
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Grant
Method, apparatus and system to interconnect packaged integrated ci...
- Patent number 10,910,347
- Issue date Feb 2, 2021
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stair-stacked dice device in a system in package, and methods of ma...
- Patent number 10,770,434
- Issue date Sep 8, 2020
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prepackaged stair-stacked memory module in a chip scale system in p...
- Patent number 10,727,208
- Issue date Jul 28, 2020
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Grant
Method, apparatus and system to interconnect packaged integrated ci...
- Patent number 10,396,055
- Issue date Aug 27, 2019
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED...
- Publication number 20220230995
- Publication date Jul 21, 2022
- Intel Corporation
- Zhijun Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FILM IN SUBSTRATE FOR RELEASING Z STACK-UP CONSTRAINT
- Publication number 20220093568
- Publication date Mar 24, 2022
- Intel Corporation
- Jianfeng HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE STACK WITH REDUCED WARPAGE
- Publication number 20220020704
- Publication date Jan 20, 2022
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE PACKAGE
- Publication number 20210265305
- Publication date Aug 26, 2021
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE FABRICATED USING LITHOGRAPHIC AND DEPOSITION...
- Publication number 20210057326
- Publication date Feb 25, 2021
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...
- Publication number 20200402961
- Publication date Dec 24, 2020
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...
- Publication number 20200357773
- Publication date Nov 12, 2020
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Application
AN NPUT DEVICE FOR INTELLIGENT TERMINAL
- Publication number 20200316460
- Publication date Oct 8, 2020
- SHANGHAI ZHONGLIAN TECHNOLOGIES LTD., CO
- Haitao DUAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AN INPUT DEVICE FOR INTELLIGENT TERMINAL, SHELL AND INTELLIGENT TER...
- Publication number 20200310556
- Publication date Oct 1, 2020
- SHANGHAI ZHONGLIAN TECHNOLOGIES LTD., CO
- Haitao DUAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED...
- Publication number 20200227387
- Publication date Jul 16, 2020
- Intel Corporation
- Zhijun Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE STACK WITH REDUCED WARPAGE
- Publication number 20200051929
- Publication date Feb 13, 2020
- Intel Corporation
- Yong She
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DIE STACKS
- Publication number 20190371766
- Publication date Dec 5, 2019
- Intel Corporation
- Bin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR WINDOWED SUBSTRATE INTEGRATED CIRCUIT PACKAGES
- Publication number 20190355700
- Publication date Nov 21, 2019
- Intel Corporation
- Aiping Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...
- Publication number 20190341372
- Publication date Nov 7, 2019
- Intel Corporation
- Yong SHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL BOND-WIRE STACKED CHIP-SCALE PACKAGE WITH APPLICATION-SPEC...
- Publication number 20190273037
- Publication date Sep 5, 2019
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...
- Publication number 20190229092
- Publication date Jul 25, 2019
- Intel Corporation
- Zhicheng Ding
- G01 - MEASURING TESTING
Information Patent Application
STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...
- Publication number 20190214370
- Publication date Jul 11, 2019
- Intel Corporation
- Zhicheng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...
- Publication number 20190019777
- Publication date Jan 17, 2019
- Intel Corporation
- Yong SHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP LIKE INTEGRATED PASSIVE PREPACKAGE FOR SIP DEVICE
- Publication number 20180374835
- Publication date Dec 27, 2018
- Intel Corporation
- Zhicheng DING
- H01 - BASIC ELECTRIC ELEMENTS

Zhicheng DING

Person

Patents Grantslast 30 patents

Film in substrate for releasing z stack-up constraint

Joint connection of corner non-critical to function (NCTF) ball for...

Power enhanced stacked chip scale package solution with integrated...

Die stack with reduced warpage

Electronic device package

Interconnect structure fabricated using lithographic and deposition...

Vertical bond-wire stacked chip-scale package with application-spec...

Power enhanced stacked chip scale package solution with integrated...

Input device for intelligent terminal

Flip-chip like integrated passive prepackage for SIP device

Die stack with reduced warpage

Stair-stacked dice device in a system in package, and methods of ma...

Prepackaged stair-stacked memory module in a chip scale system in p...

Method, apparatus and system to interconnect packaged integrated ci...

Stair-stacked dice device in a system in package, and methods of ma...

Prepackaged stair-stacked memory module in a chip scale system in p...

Method, apparatus and system to interconnect packaged integrated ci...

Patents Applicationslast 30 patents

POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED...

FILM IN SUBSTRATE FOR RELEASING Z STACK-UP CONSTRAINT

DIE STACK WITH REDUCED WARPAGE

ELECTRONIC DEVICE PACKAGE

INTERCONNECT STRUCTURE FABRICATED USING LITHOGRAPHIC AND DEPOSITION...

STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...

PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...

AN NPUT DEVICE FOR INTELLIGENT TERMINAL

AN INPUT DEVICE FOR INTELLIGENT TERMINAL, SHELL AND INTELLIGENT TER...

POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED...

DIE STACK WITH REDUCED WARPAGE

INTEGRATED CIRCUIT DIE STACKS

TECHNIQUES FOR WINDOWED SUBSTRATE INTEGRATED CIRCUIT PACKAGES

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...

VERTICAL BOND-WIRE STACKED CHIP-SCALE PACKAGE WITH APPLICATION-SPEC...

PREPACKAGED STAIR-STACKED MEMORY MODULE IN A CHIP SCALE SYSTEM IN P...

STAIR-STACKED DICE DEVICE IN A SYSTEM IN PACKAGE, AND METHODS OF MA...

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...

FLIP-CHIP LIKE INTEGRATED PASSIVE PREPACKAGE FOR SIP DEVICE