Zhiyong Wang

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timing optimization of memory blocks in a programmable IC
- Patent number 10,699,053
- Issue date Jun 30, 2020
- Xilinx, Inc.
- Zhiyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis within placement
- Patent number 10,572,621
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Zhiyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis for multi-die integrated circuit technology
- Patent number 10,496,777
- Issue date Dec 3, 2019
- Xilinx, Inc.
- Sreesan Venkatakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical and physical optimizations for partial reconfiguration desi...
- Patent number 10,303,648
- Issue date May 28, 2019
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fanout optimization to facilitate timing improvement in circuit des...
- Patent number 9,965,581
- Issue date May 8, 2018
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement and pre-routing processing of critical paths in a ci...
- Patent number 9,773,083
- Issue date Sep 26, 2017
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-routing structural netlist optimization for circuit designs
- Patent number 9,646,126
- Issue date May 9, 2017
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive multi-step physical synthesis
- Patent number 9,613,173
- Issue date Apr 4, 2017
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opportunistic candidate path selection during physical optimization...
- Patent number 9,483,597
- Issue date Nov 1, 2016
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective addition of clock buffers to a circuit design
- Patent number 9,235,660
- Issue date Jan 12, 2016
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical optimization for timing closure for an integrated circuit
- Patent number 8,984,462
- Issue date Mar 17, 2015
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS
- Publication number 20170098024
- Publication date Apr 6, 2017
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING

Zhiyong Wang

Person

Patents Grantslast 30 patents

Timing optimization of memory blocks in a programmable IC

Physical synthesis within placement

Physical synthesis for multi-die integrated circuit technology

Logical and physical optimizations for partial reconfiguration desi...

Fanout optimization to facilitate timing improvement in circuit des...

Post-placement and pre-routing processing of critical paths in a ci...

Post-routing structural netlist optimization for circuit designs

Interactive multi-step physical synthesis

Opportunistic candidate path selection during physical optimization...

Selective addition of clock buffers to a circuit design

Physical optimization for timing closure for an integrated circuit

Patents Applicationslast 30 patents

INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS