Zhizheng Liu

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Barrier region underlying source/drain regions for dual-bit memory...
- Patent number 9,171,936
- Issue date Oct 27, 2015
- Cypress Semiconductor Corporation
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjacent wordline disturb reduction using boron/indium implant
- Patent number 9,153,596
- Issue date Oct 6, 2015
- Cypress Semiconductor Corporation
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Screening for reference cells in a memory
- Patent number 9,142,311
- Issue date Sep 22, 2015
- Cypress Semiconductor Corporation
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-pass soft programming
- Patent number 8,995,198
- Issue date Mar 31, 2015
- Spansion LLC
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 8,559,255
- Issue date Oct 15, 2013
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Strapping contact for charge protection
- Patent number 8,404,541
- Issue date Mar 26, 2013
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 8,264,898
- Issue date Sep 11, 2012
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for reducing process-induced charging
- Patent number 8,203,178
- Issue date Jun 19, 2012
- Spansion LLC
- Ashot Melik Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Applying negative gate voltage to wordlines adjacent to wordline as...
- Patent number 7,995,386
- Issue date Aug 9, 2011
- Spansion LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 7,986,562
- Issue date Jul 26, 2011
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Thin oxide dummy tiling as charge protection
- Patent number 7,977,218
- Issue date Jul 12, 2011
- Spansion LLC
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,952,938
- Issue date May 31, 2011
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Room temperature drift suppression via soft program after erase
- Patent number 7,944,746
- Issue date May 17, 2011
- Spansion LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Using thick spacer for bitline implant then remove
- Patent number 7,888,218
- Issue date Feb 15, 2011
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for reducing process-induced charging
- Patent number 7,804,125
- Issue date Sep 28, 2010
- Spansion LLC
- Ashot Melik Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strapping contact for charge protection
- Patent number 7,750,407
- Issue date Jul 6, 2010
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming in memory devices using source bitline voltage bias
- Patent number 7,746,698
- Issue date Jun 29, 2010
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective application of word line bias to minimize fringe effects...
- Patent number 7,746,705
- Issue date Jun 29, 2010
- Spansion LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling AC disturbance while programming
- Patent number 7,679,967
- Issue date Mar 16, 2010
- Spansion LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Deep bitline implant to avoid program disturb
- Patent number 7,671,405
- Issue date Mar 2, 2010
- Spansion LLC
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-phase wordline erasing for flash memory
- Patent number 7,626,869
- Issue date Dec 1, 2009
- Spansion LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Algorithm for charge loss reduction and Vt distribution improvement
- Patent number 7,619,932
- Issue date Nov 17, 2009
- Spansion LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Back-to-back NPN/PNP protection diodes
- Patent number 7,573,103
- Issue date Aug 11, 2009
- Spansion LLC
- Yi He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Select transistor using buried bit line from core
- Patent number 7,561,457
- Issue date Jul 14, 2009
- Spansion LLC
- Mark Randolph
- G11 - INFORMATION STORAGE
Information Patent Grant
Using implanted poly-1 to improve charging protection in dual-poly...
- Patent number 7,553,727
- Issue date Jun 30, 2009
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for erasing and programming memory devices
- Patent number 7,394,702
- Issue date Jul 1, 2008
- Spansion LLC
- Meng Ding
- G11 - INFORMATION STORAGE
Information Patent Grant
Back-to-back NPN/PNP protection diodes
- Patent number 7,285,827
- Issue date Oct 23, 2007
- Spansion LLC
- Yi He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming a memory device
- Patent number 7,269,067
- Issue date Sep 11, 2007
- Spansion LLC
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for reducing process-induced charging
- Patent number 7,262,095
- Issue date Aug 28, 2007
- Spansion LLC
- Ashot Melik Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell and methods for programming and erasing
- Patent number 7,215,577
- Issue date May 8, 2007
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MULTI-PASS SOFT PROGRAMMING
- Publication number 20150103601
- Publication date Apr 16, 2015
- SPANSION LLC
- Gulzar A. KATHAWALA
- G11 - INFORMATION STORAGE
Information Patent Application
Screening for Reference Cells in a Memory
- Publication number 20140369141
- Publication date Dec 18, 2014
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
- Publication number 20140233339
- Publication date Aug 21, 2014
- SPANSION LLC
- Amichai GIVANT
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20120294103
- Publication date Nov 22, 2012
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20110235412
- Publication date Sep 29, 2011
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
- Publication number 20100314753
- Publication date Dec 16, 2010
- SPANSION LLC
- Ashot Melik MARTIROSIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20100240210
- Publication date Sep 23, 2010
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
- Publication number 20100213535
- Publication date Aug 26, 2010
- SPANSION LLC
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...
- Publication number 20100208527
- Publication date Aug 19, 2010
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...
- Publication number 20100128521
- Publication date May 27, 2010
- SPANSION LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20100103732
- Publication date Apr 29, 2010
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
- Publication number 20090161462
- Publication date Jun 25, 2009
- SPANSION LLC
- Sung-Yong Chung
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
- Publication number 20090154246
- Publication date Jun 18, 2009
- SPANSION LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT
- Publication number 20090154251
- Publication date Jun 18, 2009
- SPANSION LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Selective Application Of Word Line Bias To Minimize Fringe Effects...
- Publication number 20090147589
- Publication date Jun 11, 2009
- SPANSION LLC
- Gulzar Ahmed Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
- Publication number 20090135659
- Publication date May 28, 2009
- SPANSION LLC
- Gwyn Robert Jones
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
- Publication number 20080279014
- Publication date Nov 13, 2008
- SPANSION LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Using thick spacer for bitline implant then remove
- Publication number 20080153223
- Publication date Jun 26, 2008
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin oxide dummy tiling as charge protection
- Publication number 20080153269
- Publication date Jun 26, 2008
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep bitline implant to avoid program disturb
- Publication number 20080153274
- Publication date Jun 26, 2008
- Timothy Thurgate
- G11 - INFORMATION STORAGE
Information Patent Application
Using implanted poly-1 to improve charging protection in dual-poly...
- Publication number 20080150006
- Publication date Jun 26, 2008
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAPPING CONTACT FOR CHARGE PROTECTION
- Publication number 20080142889
- Publication date Jun 19, 2008
- SPANSION LLC
- Wei ZHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier region for memory devices
- Publication number 20080135902
- Publication date Jun 12, 2008
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
- Publication number 20080123384
- Publication date May 29, 2008
- SPANSION LLC
- Mark RANDOLPH
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
- Publication number 20070267686
- Publication date Nov 22, 2007
- SPANSION LLC
- Ashot Melik MARTIROSIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for erasing and programming memory devices
- Publication number 20070247923
- Publication date Oct 25, 2007
- Meng Ding
- G11 - INFORMATION STORAGE
Information Patent Application
Method for programming a memory device
- Publication number 20070008782
- Publication date Jan 11, 2007
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory cell and methods for programming and erasing
- Publication number 20060291282
- Publication date Dec 28, 2006
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Read-only memory array with dielectric breakdown programmability
- Publication number 20060268593
- Publication date Nov 30, 2006
- Spansion LLC
- Meng Ding
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory unit and method of programming a flash memory device
- Publication number 20060023511
- Publication date Feb 2, 2006
- Zhigang Wang
- G11 - INFORMATION STORAGE

Zhizheng Liu

Person

Patents Grantslast 30 patents

Barrier region underlying source/drain regions for dual-bit memory...

Adjacent wordline disturb reduction using boron/indium implant

Screening for reference cells in a memory

Multi-pass soft programming

Controlling AC disturbance while programming

Strapping contact for charge protection

Controlling AC disturbance while programming

System and method for reducing process-induced charging

Applying negative gate voltage to wordlines adjacent to wordline as...

Controlling AC disturbance while programming

Thin oxide dummy tiling as charge protection

Selective application of word line bias to minimize fringe effects...

Room temperature drift suppression via soft program after erase

Using thick spacer for bitline implant then remove

System and method for reducing process-induced charging

Strapping contact for charge protection

Programming in memory devices using source bitline voltage bias

Selective application of word line bias to minimize fringe effects...

Controlling AC disturbance while programming

Deep bitline implant to avoid program disturb

Multi-phase wordline erasing for flash memory

Algorithm for charge loss reduction and Vt distribution improvement

Back-to-back NPN/PNP protection diodes

Select transistor using buried bit line from core

Using implanted poly-1 to improve charging protection in dual-poly...

Methods for erasing and programming memory devices

Back-to-back NPN/PNP protection diodes

Programming a memory device

System and method for reducing process-induced charging

Flash memory cell and methods for programming and erasing

Patents Applicationslast 30 patents

MULTI-PASS SOFT PROGRAMMING

Screening for Reference Cells in a Memory

APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING

STRAPPING CONTACT FOR CHARGE PROTECTION

ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT

SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS...

APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS

ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT

Selective Application Of Word Line Bias To Minimize Fringe Effects...

ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE

MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY

Using thick spacer for bitline implant then remove

Thin oxide dummy tiling as charge protection

Deep bitline implant to avoid program disturb

Using implanted poly-1 to improve charging protection in dual-poly...

STRAPPING CONTACT FOR CHARGE PROTECTION

Barrier region for memory devices

SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE

SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING

Methods for erasing and programming memory devices

Method for programming a memory device

Flash memory cell and methods for programming and erasing

Read-only memory array with dielectric breakdown programmability

Flash memory unit and method of programming a flash memory device