Zhuo Li

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Driver resizing using a transition-based pin capacitance increase m...
- Patent number 11,868,695
- Issue date Jan 9, 2024
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying redundant logic based on clock gate enable condition
- Patent number 11,797,747
- Issue date Oct 24, 2023
- Cadence Design Systems, Inc.
- Matthew David Eaton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on fractional via cost and via density
- Patent number 11,734,485
- Issue date Aug 22, 2023
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pruning redundant buffering solutions using fast timing models
- Patent number 11,675,956
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing using rule-based blockage extension
- Patent number 11,675,955
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based clustering for clock tree synthesis
- Patent number 11,645,441
- Issue date May 9, 2023
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grouping cells in cell library based on clustering
- Patent number 11,625,525
- Issue date Apr 11, 2023
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-CTS clock tree restructuring
- Patent number 11,620,428
- Issue date Apr 4, 2023
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching power aware driver resizing by considering net activity i...
- Patent number 11,526,650
- Issue date Dec 13, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pruning of buffering candidates for improved efficiency of evaluation
- Patent number 11,520,959
- Issue date Dec 6, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell-width aware buffer insertion technique for narrow channels
- Patent number 11,514,222
- Issue date Nov 29, 2022
- Cadence Design Systems, Inc.
- Sheng-En David Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on routing demand adjustment
- Patent number 11,461,530
- Issue date Oct 4, 2022
- Cadence Design Systems, Inc.
- Mateus Paiva Fogaça
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-CTS clock tree restructuring with ripple move
- Patent number 11,354,479
- Issue date Jun 7, 2022
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining clock gates for decloning based on simulation and satis...
- Patent number 11,354,480
- Issue date Jun 7, 2022
- Cadence Design Systems, Ine.
- Matthew David Eaton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering algorithm with maximum cost constraint
- Patent number 11,347,923
- Issue date May 31, 2022
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Macro clock latency computation in multiple iteration clock tree sy...
- Patent number 11,321,514
- Issue date May 3, 2022
- Cadence Design Systems, Inc.
- Dirk Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based prediction method for iterative clustering d...
- Patent number 11,244,099
- Issue date Feb 8, 2022
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic weighting scheme for local cluster refinement
- Patent number 11,188,702
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generate clock network using inverting integrated clock gate
- Patent number 11,163,929
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using negative-edge integrated clock gate in clock network
- Patent number 11,132,490
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Ruth Patricia Jackson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment based on wirelength threshold
- Patent number 11,132,489
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layer assignment and routing based on resistance or capacitance cha...
- Patent number 11,080,457
- Issue date Aug 3, 2021
- Cadence Design Systems, Inc.
- Derong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Track assignment by dynamic programming
- Patent number 11,030,378
- Issue date Jun 8, 2021
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on layer-assigned net and placement blockage
- Patent number 10,997,352
- Issue date May 4, 2021
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay dependence in physically aware cell cloning
- Patent number 10,990,721
- Issue date Apr 27, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimension clock gate design in clock tree synthesis
- Patent number 10,963,618
- Issue date Mar 30, 2021
- Cadence Design Systems, Ine.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying route topology to fix clock tree violations
- Patent number 10,963,617
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer insertion technique to consider edge spacing and stack via d...
- Patent number 10,963,620
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified improvement scoring calculation for rebuffering an integrat...
- Patent number 10,936,777
- Issue date Mar 2, 2021
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Runtime efficient circuit placement search location selection
- Patent number 10,936,783
- Issue date Mar 2, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS
- Publication number 20220318480
- Publication date Oct 6, 2022
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Addressing Coupled Noise-Based Violations with Buffering in a Batch...
- Publication number 20170161407
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS
- Publication number 20160132767
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS
- Publication number 20160132765
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT-TOLERANT POWER-DRIVEN SYNTHESIS
- Publication number 20160132769
- Publication date May 12, 2016
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS
- Publication number 20150199465
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...
- Publication number 20150143326
- Publication date May 21, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE D...
- Publication number 20150113491
- Publication date Apr 23, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140223397
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140195998
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUS...
- Publication number 20140181772
- Publication date Jun 26, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...
- Publication number 20140149957
- Publication date May 29, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN
- Publication number 20140143746
- Publication date May 22, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20140101629
- Publication date Apr 10, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140088791
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140081478
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING
- Publication number 20140074389
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G08 - SIGNALLING
Information Patent Application
SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING
- Publication number 20140071827
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20130346938
- Publication date Dec 26, 2013
- International Business Machines Corporation
- Charles J Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20130326450
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK
- Publication number 20130326456
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING REFINEMENT RE-ROUTING
- Publication number 20130326458
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Michael Anthony Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
- Publication number 20130283225
- Publication date Oct 24, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONGESTION AWARE ROUTING USING RANDOM POINTS
- Publication number 20130272126
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SOLVING CONGESTION USING NET GROUPING
- Publication number 20130275934
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK
- Publication number 20130096976
- Publication date Apr 18, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...
- Publication number 20130086543
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Kanak Behari Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Routability Using Multiplexer Structures
- Publication number 20130086537
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL RO...
- Publication number 20130086544
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTI...
- Publication number 20130086545
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Driver resizing using a transition-based pin capacitance increase m...

Identifying redundant logic based on clock gate enable condition

Routing congestion based on fractional via cost and via density

Pruning redundant buffering solutions using fast timing models

Routing using rule-based blockage extension

Machine-learning based clustering for clock tree synthesis

Grouping cells in cell library based on clustering

Post-CTS clock tree restructuring

Switching power aware driver resizing by considering net activity i...

Pruning of buffering candidates for improved efficiency of evaluation

Cell-width aware buffer insertion technique for narrow channels

Circuit design routing based on routing demand adjustment

Post-CTS clock tree restructuring with ripple move

Determining clock gates for decloning based on simulation and satis...

Buffering algorithm with maximum cost constraint

Macro clock latency computation in multiple iteration clock tree sy...

Machine-learning based prediction method for iterative clustering d...

Dynamic weighting scheme for local cluster refinement

Generate clock network using inverting integrated clock gate

Using negative-edge integrated clock gate in clock network

Layer assignment based on wirelength threshold

Layer assignment and routing based on resistance or capacitance cha...

Track assignment by dynamic programming

Routing congestion based on layer-assigned net and placement blockage

Delay dependence in physically aware cell cloning

Multi-dimension clock gate design in clock tree synthesis

Modifying route topology to fix clock tree violations

Buffer insertion technique to consider edge spacing and stack via d...

Unified improvement scoring calculation for rebuffering an integrat...

Runtime efficient circuit placement search location selection

Patents Applicationslast 30 patents

PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS

Addressing Coupled Noise-Based Violations with Buffering in a Batch...

POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS

POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS

FAULT-TOLERANT POWER-DRIVEN SYNTHESIS

BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS

EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...

COMPUTER-BASED MODELING OF INTEGRATED CIRCUIT CONGESTION AND WIRE D...

Automatic Generation of Wire Tag Lists for a Metal Stack

Automatic Generation of Wire Tag Lists for a Metal Stack

DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUS...

STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...

DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN

EARLY DESIGN CYCLE OPTIMZATION

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING

SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING

POST-PLACEMENT CELL SHIFTING

EARLY DESIGN CYCLE OPTIMZATION

DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK

TIMING REFINEMENT RE-ROUTING

DATAPATH PLACEMENT USING TIERED ASSIGNMENT

CONGESTION AWARE ROUTING USING RANDOM POINTS

SOLVING CONGESTION USING NET GROUPING

COST-EFFECTIVE AND RELIABLE UTILITIES DISTRIBUTION NETWORK

MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...

Design Routability Using Multiplexer Structures

CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL RO...

EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTI...