Zicheng G. Ling

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Determination of clock path delays and implementation of a circuit...
- Patent number 10,289,784
- Issue date May 14, 2019
- Xilinx, Inc.
- Chiao K. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing circuit performance by separating device and interco...
- Patent number 7,724,016
- Issue date May 25, 2010
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Grant
Characterizing circuit performance by separating device and interco...
- Patent number 7,489,152
- Issue date Feb 10, 2009
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Grant
Characterizing circuit performance by separating device and interco...
- Patent number 7,109,734
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Grant
Testing vias and contracts in integrated circuit
- Patent number 7,046,026
- Issue date May 16, 2006
- Xilinx, Inc.
- Tai-An Chao
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating an IC mask using a reduced database
- Patent number 6,868,537
- Issue date Mar 15, 2005
- Xilinx, Inc.
- Jonathan J. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures and methods for determining the effects of high stress c...
- Patent number 6,867,580
- Issue date Mar 15, 2005
- Xilinx, Inc.
- Jan L. de Jong
- G01 - MEASURING TESTING
Information Patent Grant
Structures and methods for determining the effects of high stress c...
- Patent number 6,842,019
- Issue date Jan 11, 2005
- Xilinx, Inc.
- Jan L. de Jong
- G01 - MEASURING TESTING
Information Patent Grant
Testing vias and contacts in an integrated circuit
- Patent number 6,784,685
- Issue date Aug 31, 2004
- Xilinx, Inc.
- Tai-An Chao
- G01 - MEASURING TESTING
Information Patent Grant
Structures and methods for determining the effects of high stress c...
- Patent number 6,727,710
- Issue date Apr 27, 2004
- Xilinx, Inc.
- Jan L. de Jong
- G01 - MEASURING TESTING
Information Patent Grant
Method of fabricating ultra shallow junction CMOS transistors with...
- Patent number 6,551,870
- Issue date Apr 22, 2003
- Advanced Micro Devices, Inc.
- Zicheng Gary Ling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing vias and contacts in integrated circuit fabrication
- Patent number 6,503,765
- Issue date Jan 7, 2003
- Xilinx, Inc.
- Tai-An Chao
- G01 - MEASURING TESTING
Information Patent Grant
Exposure correction based on reflective index for photolithographic...
- Patent number 6,482,573
- Issue date Nov 19, 2002
- Advanced Micro Devices, Inc.
- Jayendra D. Bhakta
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduced masking step CMOS transistor formation using removable amor...
- Patent number 6,479,350
- Issue date Nov 12, 2002
- Advanced Micro Devices, Inc.
- Zicheng Gary Ling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active mask exposure compensation of underlying nitride thickness v...
- Patent number 6,368,762
- Issue date Apr 9, 2002
- Advanced Micro Devices, Inc.
- Zicheng Gary Ling
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual spacer method of forming CMOS transistors with substantially t...
- Patent number 6,306,702
- Issue date Oct 23, 2001
- Advanced Micro Devices, Inc.
- Ming Yin Hao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two step mask process to eliminate gate end cap shortening
- Patent number 6,287,904
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Raymond T. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum disposable spacer to reduce mask count in CMOS transistor...
- Patent number 6,265,253
- Issue date Jul 24, 2001
- Advanced Micro Devices, Inc.
- Todd Lukanc
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum disposable spacer to reduce mask count in CMOS transistor...
- Patent number 6,221,706
- Issue date Apr 24, 2001
- Advanced Micro Devices, Inc.
- Todd Lukanc
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitride disposable spacer to reduce mask count in CMOS transistor f...
- Patent number 6,218,224
- Issue date Apr 17, 2001
- Advanced Micro Devices, Inc.
- Todd Lukanc
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Amorphous silicon disposable spacer to reduce mask count in CMOS tr...
- Patent number 6,214,655
- Issue date Apr 10, 2001
- Advanced Micro Devices, Inc.
- Raymond T. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for measuring gate length and drain/source gate overlap
- Patent number 6,166,558
- Issue date Dec 26, 2000
- Advanced Micro Devices, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating ultra shallow junction CMOS transistors with...
- Patent number 6,153,455
- Issue date Nov 28, 2000
- Advanced Micro Devices
- Zicheng Gary Ling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitride disposable spacer to reduce mask count in CMOS transistor f...
- Patent number 6,103,563
- Issue date Aug 15, 2000
- Advanced Micro Devices, Inc.
- Todd Lukanc
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCO...
- Publication number 20090121737
- Publication date May 14, 2009
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Characterizing circuit performance by separating device and interco...
- Publication number 20060267618
- Publication date Nov 30, 2006
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Characterizing circuit performance by separating device and interco...
- Publication number 20050149777
- Publication date Jul 7, 2005
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Testing vias and contacts in integrated circuit
- Publication number 20040257105
- Publication date Dec 23, 2004
- Xilinx, Inc.
- Tai-An Chao
- G01 - MEASURING TESTING
Information Patent Application
Testing vias and contacts in integrated circuit fabrication
- Publication number 20030025516
- Publication date Feb 6, 2003
- Xilinx, Inc.
- Tai-An Chao
- G01 - MEASURING TESTING

Zicheng G. Ling

Person

Patents Grantslast 30 patents

Determination of clock path delays and implementation of a circuit...

Characterizing circuit performance by separating device and interco...

Characterizing circuit performance by separating device and interco...

Characterizing circuit performance by separating device and interco...

Testing vias and contracts in integrated circuit

Method of generating an IC mask using a reduced database

Structures and methods for determining the effects of high stress c...

Structures and methods for determining the effects of high stress c...

Testing vias and contacts in an integrated circuit

Structures and methods for determining the effects of high stress c...

Method of fabricating ultra shallow junction CMOS transistors with...

Testing vias and contacts in integrated circuit fabrication

Exposure correction based on reflective index for photolithographic...

Reduced masking step CMOS transistor formation using removable amor...

Active mask exposure compensation of underlying nitride thickness v...

Dual spacer method of forming CMOS transistors with substantially t...

Two step mask process to eliminate gate end cap shortening

Aluminum disposable spacer to reduce mask count in CMOS transistor...

Aluminum disposable spacer to reduce mask count in CMOS transistor...

Nitride disposable spacer to reduce mask count in CMOS transistor f...

Amorphous silicon disposable spacer to reduce mask count in CMOS tr...

Method for measuring gate length and drain/source gate overlap

Method of fabricating ultra shallow junction CMOS transistors with...

Nitride disposable spacer to reduce mask count in CMOS transistor f...

Patents Applicationslast 30 patents

CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCO...

Characterizing circuit performance by separating device and interco...

Characterizing circuit performance by separating device and interco...

Testing vias and contacts in integrated circuit

Testing vias and contacts in integrated circuit fabrication