Ziyad Hakura

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power efficient attribute handling for tessellation and geometry sh...
- Patent number 11,663,767
- Issue date May 30, 2023
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rendering scenes using a combination of raytracing and rasterization
- Patent number 11,468,630
- Issue date Oct 11, 2022
- NVIDIA Corporation
- Christoph Kubisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling cache traffic in a tile-based architecture
- Patent number 11,107,176
- Issue date Aug 31, 2021
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for ordering atomic operations
- Patent number 11,016,802
- Issue date May 25, 2021
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for representing and processing geometry within an expan...
- Patent number 10,909,739
- Issue date Feb 2, 2021
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for pre-processing index buffers for a graphics processi...
- Patent number 10,878,611
- Issue date Dec 29, 2020
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-generated stable barycentric coordinates and direct plane eq...
- Patent number 10,861,230
- Issue date Dec 8, 2020
- NVIDIA Corporation
- David Patrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rendering scenes using a combination of raytracing and rasterization
- Patent number 10,853,994
- Issue date Dec 1, 2020
- NVIDIA Corporation
- Christoph Kubisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for representing and processing geometry within a graphi...
- Patent number 10,600,229
- Issue date Mar 24, 2020
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data structures for efficient tiled rendering
- Patent number 10,489,875
- Issue date Nov 26, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for maintaining atomicity and ordering for pixel shader...
- Patent number 10,453,168
- Issue date Oct 22, 2019
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-pass cache tile processing for visibility testing in a tile-bas...
- Patent number 10,438,314
- Issue date Oct 8, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-pass rendering in a screen space pipeline
- Patent number 10,430,989
- Issue date Oct 1, 2019
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed index fetch, primitive assembly, and primitive batching
- Patent number 10,332,310
- Issue date Jun 25, 2019
- NVIDIA Corporation
- Niket Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State handling in a tiled architecture
- Patent number 10,282,803
- Issue date May 7, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing event count reports in a tile-based architecture
- Patent number 10,223,122
- Issue date Mar 5, 2019
- NVIDIA Corporation
- Ziyad S. Hakura
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Multi-pass rendering in a screen space pipeline
- Patent number 10,147,222
- Issue date Dec 4, 2018
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-frame scanout for latency reduction in virtual reality applicat...
- Patent number 10,120,187
- Issue date Nov 6, 2018
- NVIDIA Corporation
- Craig Michael Wittenbrink
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for managing graphics processing resources in a tile-bas...
- Patent number 10,083,036
- Issue date Sep 25, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for executing processe...
- Patent number 10,078,911
- Issue date Sep 18, 2018
- NVIDIA Corporation
- Ziyad Sami Hakura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Stereo multi-projection implemented using a graphics processing pip...
- Patent number 10,068,366
- Issue date Sep 4, 2018
- NVIDIA Corporation
- Ziyad Sami Hakura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for maintaining atomicity and ordering for pixel shader...
- Patent number 10,055,806
- Issue date Aug 21, 2018
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for maintaining atomicity and ordering for pixel shader...
- Patent number 10,032,245
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing deferred contexts in a cache tiling architecture
- Patent number 10,032,242
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed tiled caching
- Patent number 10,032,243
- Issue date Jul 24, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for maintaining atomicity and ordering for pixel shader...
- Patent number 10,019,776
- Issue date Jul 10, 2018
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-pass cache tile processing for visibility testing in a tile-bas...
- Patent number 9,952,868
- Issue date Apr 24, 2018
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for processing primiti...
- Patent number 9,836,878
- Issue date Dec 5, 2017
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting downstream render state in an upstream shader
- Patent number 9,830,741
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Emmett M. Kilgariff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for improving performance in a tile based architecture
- Patent number 9,792,122
- Issue date Oct 17, 2017
- NVIDIA Corporation
- Ziyad S. Hakura
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HEURISTICS ENABLED TILED RENDERING
- Publication number 20230360305
- Publication date Nov 9, 2023
- NVIDIA Corporation
- Ziyad Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RENDERING SCENES USING A COMBINATION OF RAYTRACING AND RASTERIZATION
- Publication number 20210082177
- Publication date Mar 18, 2021
- NVIDIA Corporation
- Christoph Kubisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RENDERING SCENES USING A COMBINATION OF RAYTRACING AND RASTERIZATION
- Publication number 20200372703
- Publication date Nov 26, 2020
- NVIDIA Corporation
- Christoph Kubisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-GENERATED STABLE BARYCENTRIC COORDINATES AND DIRECT PLANE EQ...
- Publication number 20200043228
- Publication date Feb 6, 2020
- NVIDIA Corporation
- David Patrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-PASS CACHE TILE PROCESSING FOR VISIBILITY TESTING IN A TILE-BAS...
- Publication number 20190243652
- Publication date Aug 8, 2019
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR REPRESENTING AND PROCESSING GEOMETRY WITHIN A GRAPHI...
- Publication number 20190236827
- Publication date Aug 1, 2019
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ORDERING ATOMIC OPERATIONS
- Publication number 20190235915
- Publication date Aug 1, 2019
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PRE-PROCESSING INDEX BUFFERS FOR A GRAPHICS PROCESSI...
- Publication number 20190236829
- Publication date Aug 1, 2019
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR REPRESENTING AND PROCESSING GEOMETRY WITHIN AN EXPAN...
- Publication number 20190236828
- Publication date Aug 1, 2019
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for maintaining atomicity and ordering for pixel shader...
- Publication number 20180374185
- Publication date Dec 27, 2018
- NVIDIA Corporation
- ZIYAD HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-PASS CACHE TILE PROCESSING FOR VISIBILITY TESTING IN A TILE-BAS...
- Publication number 20180307490
- Publication date Oct 25, 2018
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STEREO MULTI-PROJECTION IMPLEMENTED USING A GRAPHICS PROCESSING PIP...
- Publication number 20170323469
- Publication date Nov 9, 2017
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUB-FRAME SCANOUT FOR LATENCY REDUCTION IN VIRTUAL REALITY APPLICAT...
- Publication number 20170243319
- Publication date Aug 24, 2017
- NVIDIA Corporation
- Craig Michael Wittenbrink
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING EVENT COUNT REPORTS IN A TILE-BASED ARCHITECTURE
- Publication number 20170213313
- Publication date Jul 27, 2017
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE
- Publication number 20170206623
- Publication date Jul 20, 2017
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING
- Publication number 20170178401
- Publication date Jun 22, 2017
- NVIDIA Corporation
- Niket Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE
- Publication number 20170148203
- Publication date May 25, 2017
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE
- Publication number 20170148204
- Publication date May 25, 2017
- NVIDIA Corporation
- Ziyad HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...
- Publication number 20170116700
- Publication date Apr 27, 2017
- NVIDIA Corporation
- ZIYAD HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...
- Publication number 20170116698
- Publication date Apr 27, 2017
- NVIDIA Corporation
- ZIYAD HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...
- Publication number 20170116699
- Publication date Apr 27, 2017
- NVIDIA Corporation
- ZIYAD HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING
- Publication number 20170046812
- Publication date Feb 16, 2017
- NVIDIA Corporation
- Eric Brian Lum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING PRIMITI...
- Publication number 20150348317
- Publication date Dec 3, 2015
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL TILED CACHING
- Publication number 20150213638
- Publication date Jul 30, 2015
- NVIDIA Corporation
- Rouslan DIMITROV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE-BASED ARCHITECTURE
- Publication number 20150097845
- Publication date Apr 9, 2015
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PASSING ATTRIBUTE...
- Publication number 20150054827
- Publication date Feb 26, 2015
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING PROCESSE...
- Publication number 20140267260
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR IMPROVING THE PERFORMANCE OF A TESSELLATION PIPELINE
- Publication number 20140267320
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GENERATING PRIMITI...
- Publication number 20140267276
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Ziyad Sami Hakura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR IMPROVING THE PERFORMANCE OF A TESSELLATION PIPELINE
- Publication number 20140267319
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Ziyad S. HAKURA
- G06 - COMPUTING CALCULATING COUNTING

Ziyad Hakura

Person

Patents Grantslast 30 patents

Power efficient attribute handling for tessellation and geometry sh...

Rendering scenes using a combination of raytracing and rasterization

Scheduling cache traffic in a tile-based architecture

Techniques for ordering atomic operations

Techniques for representing and processing geometry within an expan...

Techniques for pre-processing index buffers for a graphics processi...

System-generated stable barycentric coordinates and direct plane eq...

Rendering scenes using a combination of raytracing and rasterization

Techniques for representing and processing geometry within a graphi...

Data structures for efficient tiled rendering

Techniques for maintaining atomicity and ordering for pixel shader...

Two-pass cache tile processing for visibility testing in a tile-bas...

Multi-pass rendering in a screen space pipeline

Distributed index fetch, primitive assembly, and primitive batching

State handling in a tiled architecture

Managing event count reports in a tile-based architecture

Multi-pass rendering in a screen space pipeline

Sub-frame scanout for latency reduction in virtual reality applicat...

Techniques for managing graphics processing resources in a tile-bas...

System, method, and computer program product for executing processe...

Stereo multi-projection implemented using a graphics processing pip...

Techniques for maintaining atomicity and ordering for pixel shader...

Techniques for maintaining atomicity and ordering for pixel shader...

Managing deferred contexts in a cache tiling architecture

Distributed tiled caching

Techniques for maintaining atomicity and ordering for pixel shader...

Two-pass cache tile processing for visibility testing in a tile-bas...

System, method, and computer program product for processing primiti...

Setting downstream render state in an upstream shader

Heuristics for improving performance in a tile based architecture

Patents Applicationslast 30 patents

HEURISTICS ENABLED TILED RENDERING

RENDERING SCENES USING A COMBINATION OF RAYTRACING AND RASTERIZATION

RENDERING SCENES USING A COMBINATION OF RAYTRACING AND RASTERIZATION

SYSTEM-GENERATED STABLE BARYCENTRIC COORDINATES AND DIRECT PLANE EQ...

TWO-PASS CACHE TILE PROCESSING FOR VISIBILITY TESTING IN A TILE-BAS...

TECHNIQUES FOR REPRESENTING AND PROCESSING GEOMETRY WITHIN A GRAPHI...

TECHNIQUES FOR ORDERING ATOMIC OPERATIONS

TECHNIQUES FOR PRE-PROCESSING INDEX BUFFERS FOR A GRAPHICS PROCESSI...

TECHNIQUES FOR REPRESENTING AND PROCESSING GEOMETRY WITHIN AN EXPAN...

Techniques for maintaining atomicity and ordering for pixel shader...

TWO-PASS CACHE TILE PROCESSING FOR VISIBILITY TESTING IN A TILE-BAS...

STEREO MULTI-PROJECTION IMPLEMENTED USING A GRAPHICS PROCESSING PIP...

SUB-FRAME SCANOUT FOR LATENCY REDUCTION IN VIRTUAL REALITY APPLICAT...

MANAGING EVENT COUNT REPORTS IN A TILE-BASED ARCHITECTURE

MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE

DISTRIBUTED INDEX FETCH, PRIMITIVE ASSEMBLY, AND PRIMITIVE BATCHING

MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE

MULTI-PASS RENDERING IN A SCREEN SPACE PIPELINE

TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...

TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...

TECHNIQUES FOR MAINTAINING ATOMICITY AND ORDERING FOR PIXEL SHADER...

CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING PRIMITI...

HIERARCHICAL TILED CACHING

HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE-BASED ARCHITECTURE

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PASSING ATTRIBUTE...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING PROCESSE...

TECHNIQUE FOR IMPROVING THE PERFORMANCE OF A TESSELLATION PIPELINE

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GENERATING PRIMITI...

TECHNIQUE FOR IMPROVING THE PERFORMANCE OF A TESSELLATION PIPELINE