Ziyad Hanna

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
System, method, and computer program product for sequential equival...
- Patent number 10,984,161
- Issue date Apr 20, 2021
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for automatically infe...
- Patent number 10,983,758
- Issue date Apr 20, 2021
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for generating a forma...
- Patent number 10,789,404
- Issue date Sep 29, 2020
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional property ranking
- Patent number 9,460,252
- Issue date Oct 4, 2016
- Jasper Design Automation, Inc.
- Asa Ben-Tzur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guided exploration of circuit design states
- Patent number 9,372,949
- Issue date Jun 21, 2016
- Cadence Design Systems, Inc.
- Ziyad Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics for circuit design properties
- Patent number 9,177,089
- Issue date Nov 3, 2015
- Cadence Design Systems, Inc.
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics of covered events for circuit...
- Patent number 9,158,874
- Issue date Oct 13, 2015
- Cadence Design Systems, Inc.
- Rajeev K. Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraining traces in formal verification
- Patent number 8,863,049
- Issue date Oct 14, 2014
- Jasper Design Automation, Inc.
- Lars Lundgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics for circuit design properties
- Patent number 8,826,201
- Issue date Sep 2, 2014
- Jasper Design Automation, Inc.
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional property ranking
- Patent number 8,739,092
- Issue date May 27, 2014
- Jasper Design Automation, Inc.
- Asa Ben-Tzur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification using simultaneous and inductive SAT algorithms
- Patent number 7,730,436
- Issue date Jun 1, 2010
- Intel Corporation
- Zurab Khasidashvili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cut-point frontier selection and for count...
- Patent number 7,159,201
- Issue date Jan 2, 2007
- Intel Corporation
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application of the retimed normal form to the formal equivalence ve...
- Patent number 7,117,465
- Issue date Oct 3, 2006
- Intel Corporation
- Zurab Khasidashvili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method for VLSI design analysis
- Patent number 7,073,141
- Issue date Jul 4, 2006
- Intel Corporation
- Alexander Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cut-point frontier selection and for count...
- Patent number 6,792,581
- Issue date Sep 14, 2004
- Intel Corporation
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for verification of VLSI designs
- Patent number 6,567,959
- Issue date May 20, 2003
- Intel Corporation
- Alexander Levin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for formal verification of a circuit model using...
- Patent number 6,564,358
- Issue date May 13, 2003
- Intel Corporation
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES
- Publication number 20150135150
- Publication date May 14, 2015
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION USING SIMULTANEOUS AND INDUCTIVE SAT ALGORITHMS
- Publication number 20080103750
- Publication date May 1, 2008
- Zurab Khasidashvili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device, system and method for VLSI design analysis
- Publication number 20050114805
- Publication date May 26, 2005
- Alexander Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for cut-point frontier selection and for count...
- Publication number 20050005251
- Publication date Jan 6, 2005
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Application of the retimed normal form to the formal equivalence ve...
- Publication number 20040268274
- Publication date Dec 30, 2004
- Intel Corporation
- Zurab Khasidashvili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for cut-point frontier selection and for count...
- Publication number 20040093574
- Publication date May 13, 2004
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and device for verification of VLSI designs
- Publication number 20020144218
- Publication date Oct 3, 2002
- Alexander Levin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for formal verification of a circuit model
- Publication number 20020108093
- Publication date Aug 8, 2002
- Intel Corporation
- John Moondanos
- G06 - COMPUTING CALCULATING COUNTING

Ziyad Hanna

Person

Patents Grantslast 30 patents

System, method, and computer program product for sequential equival...

System, method, and computer program product for automatically infe...

System, method, and computer program product for generating a forma...

Functional property ranking

Guided exploration of circuit design states

Formal verification coverage metrics for circuit design properties

Formal verification coverage metrics of covered events for circuit...

Constraining traces in formal verification

Formal verification coverage metrics for circuit design properties

Functional property ranking

Verification using simultaneous and inductive SAT algorithms

Method and apparatus for cut-point frontier selection and for count...

Application of the retimed normal form to the formal equivalence ve...

Device, system and method for VLSI design analysis

Method and apparatus for cut-point frontier selection and for count...

Method and device for verification of VLSI designs

Method and system for formal verification of a circuit model using...

Patents Applicationslast 30 patents

FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES

VERIFICATION USING SIMULTANEOUS AND INDUCTIVE SAT ALGORITHMS

Device, system and method for VLSI design analysis

Method and apparatus for cut-point frontier selection and for count...

Application of the retimed normal form to the formal equivalence ve...

Method and apparatus for cut-point frontier selection and for count...

Method and device for verification of VLSI designs

Method and system for formal verification of a circuit model