Zuhair Bokharey

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 11,495,568
- Issue date Nov 8, 2022
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC package design and methodology to compensate for die-substrate C...
- Patent number 10,943,882
- Issue date Mar 9, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing a printed circuit board having high densi...
- Patent number 10,219,387
- Issue date Feb 26, 2019
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stiffening electronic packages by disposing a stiffener ring betwee...
- Patent number 9,760,132
- Issue date Sep 12, 2017
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open solder mask and or dielectric to increase lid or ring thicknes...
- Patent number 9,716,051
- Issue date Jul 25, 2017
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset integrated circuit packaging interconnects
- Patent number 9,478,482
- Issue date Oct 25, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable-size solder bump structures for integrated circuit packaging
- Patent number 9,385,098
- Issue date Jul 5, 2016
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate build up layer to achieve both finer design rule and bett...
- Patent number 9,368,439
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Absorbing excess under-fill flow with a solder trench
- Patent number 9,368,422
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System, method, and computer program product for affixing a post to...
- Patent number 9,087,830
- Issue date Jul 21, 2015
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210151403
- Publication date May 20, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...
- Publication number 20210066227
- Publication date Mar 4, 2021
- NVIDIA Corporation
- Jayprakash Chipalkatti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STIFFENING ELECTRONIC PACKAGES
- Publication number 20150077918
- Publication date Mar 19, 2015
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...
- Publication number 20140208590
- Publication date Jul 31, 2014
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH
- Publication number 20140175681
- Publication date Jun 26, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING
- Publication number 20140138823
- Publication date May 22, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS
- Publication number 20140138824
- Publication date May 22, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE BUILD UP LAYER TO ACHIEVE BOTH FINER DESIGN RULE AND BETT...
- Publication number 20140124944
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...
- Publication number 20140124913
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...
- Publication number 20140124254
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED INTEGRATED CIRCUIT PACKAGE LID HEIGHT
- Publication number 20140117527
- Publication date May 1, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING SUBSTRATE WITH RELIABLE VIA STRUCTURE
- Publication number 20130313720
- Publication date Nov 28, 2013
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...
- Publication number 20130256873
- Publication date Oct 3, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...
- Publication number 20130251967
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...
- Publication number 20130252414
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS

Zuhair Bokharey

Person

Patents Grantslast 30 patents

IC package design and methodology to compensate for die-substrate C...

IC package design and methodology to compensate for die-substrate C...

Process for manufacturing a printed circuit board having high densi...

Stiffening electronic packages by disposing a stiffener ring betwee...

Open solder mask and or dielectric to increase lid or ring thicknes...

Offset integrated circuit packaging interconnects

Variable-size solder bump structures for integrated circuit packaging

Substrate build up layer to achieve both finer design rule and bett...

Absorbing excess under-fill flow with a solder trench

System, method, and computer program product for affixing a post to...

Patents Applicationslast 30 patents

IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...

IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE C...

STIFFENING ELECTRONIC PACKAGES

PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...

ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH

VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING

OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS

SUBSTRATE BUILD UP LAYER TO ACHIEVE BOTH FINER DESIGN RULE AND BETT...

OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...

NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...

REDUCED INTEGRATED CIRCUIT PACKAGE LID HEIGHT

PACKAGING SUBSTRATE WITH RELIABLE VIA STRUCTURE

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...