Zuoguo WU

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock-gating in die-to-die (D2D) interconnects
- Patent number 12,362,306
- Issue date Jul 15, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compliance and debug testing of a die-to-die interconnect
- Patent number 12,353,305
- Issue date Jul 8, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-to-die interconnect
- Patent number 12,332,826
- Issue date Jun 17, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sideband interface for die-to-die interconnects
- Patent number 12,321,305
- Issue date Jun 3, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PHY-based retry techniques for die-to-die interfaces
- Patent number 12,316,343
- Issue date May 27, 2025
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus, method, and system for performing error correction based...
- Patent number 12,283,994
- Issue date Apr 22, 2025
- Intel Corporation
- Zuoguo Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Near field wireless communication system for mother to package and...
- Patent number 12,196,807
- Issue date Jan 14, 2025
- Intel Corporation
- Zhen Zhou
- G01 - MEASURING TESTING
Information Patent Grant
Characterizing and margining multi-voltage signal encoding for inte...
- Patent number 12,155,474
- Issue date Nov 26, 2024
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Approximate data bus inversion technique for latency sensitive appl...
- Patent number 12,117,960
- Issue date Oct 15, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 11,797,378
- Issue date Oct 24, 2023
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI express enhancements
- Patent number 11,632,130
- Issue date Apr 18, 2023
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,599,497
- Issue date Mar 7, 2023
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit package with test circuitry for testing a channe...
- Patent number 11,450,613
- Issue date Sep 20, 2022
- Intel Corporation
- Mayue Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extending multichip package link off package
- Patent number 11,386,033
- Issue date Jul 12, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 11,307,928
- Issue date Apr 19, 2022
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI express enhancements
- Patent number 11,283,466
- Issue date Mar 22, 2022
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending multichip package link off package
- Patent number 11,113,225
- Issue date Sep 7, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Discrete circuit having cross-talk noise cancellation circuitry and...
- Patent number 11,116,072
- Issue date Sep 7, 2021
- Intel Corporation
- Jun Liao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multichip package link error detection
- Patent number 11,061,761
- Issue date Jul 13, 2021
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI express enhancements
- Patent number 11,043,965
- Issue date Jun 22, 2021
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 11,003,610
- Issue date May 11, 2021
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connector with active circuit
- Patent number 10,965,047
- Issue date Mar 30, 2021
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Characterization of transmission media
- Patent number 10,908,206
- Issue date Feb 2, 2021
- Intel Corporation
- Mayue Xie
- G01 - MEASURING TESTING
Information Patent Grant
Inter-die passive interconnects approaching monolithic performance
- Patent number 10,854,548
- Issue date Dec 1, 2020
- Intel Corporation
- Zuoguo Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage modulated control lane
- Patent number 10,846,258
- Issue date Nov 24, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 10,789,201
- Issue date Sep 29, 2020
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending multichip package link off package
- Patent number 10,678,736
- Issue date Jun 9, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, system for centering in a high performance inter...
- Patent number 10,560,081
- Issue date Feb 11, 2020
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 10,552,253
- Issue date Feb 4, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 10,552,357
- Issue date Feb 4, 2020
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...
- Publication number 20250158738
- Publication date May 15, 2025
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NEAR FIELD WIRELESS COMMUNICATION SYSTEM FOR MOTHER TO PACKAGE AND...
- Publication number 20250093413
- Publication date Mar 20, 2025
- Intel Corporation
- Zhen ZHOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20240020259
- Publication date Jan 18, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE STACKING PACKAGE ARCHITECTURE FOR HIGH-SPEED INPUT/OUTPUT WITH...
- Publication number 20230369289
- Publication date Nov 16, 2023
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20230073807
- Publication date Mar 9, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK ERROR DETECTION
- Publication number 20220350698
- Publication date Nov 3, 2022
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
- Publication number 20220318111
- Publication date Oct 6, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
- Publication number 20220271912
- Publication date Aug 25, 2022
- Gerald Pasdast
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220262756
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220261308
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PCI EXPRESS ENHANCEMENTS
- Publication number 20220255559
- Publication date Aug 11, 2022
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
- Publication number 20220237138
- Publication date Jul 28, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS
- Publication number 20220222198
- Publication date Jul 14, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEAR FIELD WIRELESS COMMUNICATION SYSTEM FOR MOTHER TO PACKAGE AND...
- Publication number 20220206064
- Publication date Jun 30, 2022
- Intel Corporation
- Zhen ZHOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALTERNATE PHYSICAL LAYER POWER MODE
- Publication number 20220011849
- Publication date Jan 13, 2022
- Intel Corporation
- Michelle C. Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
- Publication number 20210344354
- Publication date Nov 4, 2021
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS, METHOD, AND SYSTEM FOR PERFORMING ERROR CORRECTION BASED...
- Publication number 20210320722
- Publication date Oct 14, 2021
- Intel Corporation
- Zuoguo Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SKEW DETECTION AND COMPENSATION FOR HIGH SPEED I/O LINKS
- Publication number 20210311120
- Publication date Oct 7, 2021
- Intel Corporation
- Jong-Ru Guo
- G01 - MEASURING TESTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20210097015
- Publication date Apr 1, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...
- Publication number 20210050941
- Publication date Feb 18, 2021
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...
- Publication number 20210004347
- Publication date Jan 7, 2021
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20200409896
- Publication date Dec 31, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Clock-gating in die-to-die (D2D) interconnects

Compliance and debug testing of a die-to-die interconnect

Die-to-die interconnect

Sideband interface for die-to-die interconnects

PHY-based retry techniques for die-to-die interfaces

Apparatus, method, and system for performing error correction based...

Near field wireless communication system for mother to package and...

Characterizing and margining multi-voltage signal encoding for inte...

Approximate data bus inversion technique for latency sensitive appl...

Multichip package link error detection

PCI express enhancements

High performance interconnect

Integrated circuit package with test circuitry for testing a channe...

Extending multichip package link off package

Multichip package link error detection

PCI express enhancements

Extending multichip package link off package

Discrete circuit having cross-talk noise cancellation circuitry and...

Multichip package link error detection

PCI express enhancements

Multichip package link

Connector with active circuit

Characterization of transmission media

Inter-die passive interconnects approaching monolithic performance

Voltage modulated control lane

High performance interconnect

Extending multichip package link off package

Method, apparatus, system for centering in a high performance inter...

Multichip package link error detection

Multichip package link

Patents Applicationslast 30 patents

CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...

NEAR FIELD WIRELESS COMMUNICATION SYSTEM FOR MOTHER TO PACKAGE AND...

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

DIE STACKING PACKAGE ARCHITECTURE FOR HIGH-SPEED INPUT/OUTPUT WITH...

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

MULTICHIP PACKAGE LINK ERROR DETECTION

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS

COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT

CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT

CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS

VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS

PCI EXPRESS ENHANCEMENTS

LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT

SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS

NEAR FIELD WIRELESS COMMUNICATION SYSTEM FOR MOTHER TO PACKAGE AND...

ALTERNATE PHYSICAL LAYER POWER MODE

PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES

APPARATUS, METHOD, AND SYSTEM FOR PERFORMING ERROR CORRECTION BASED...

SKEW DETECTION AND COMPENSATION FOR HIGH SPEED I/O LINKS

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...

APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE