ZVIKA GREENFIELD

Person

Kfar Sava, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-level system memory with near memory capable of storing compr...
- Patent number 11,188,467
- Issue date Nov 30, 2021
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically changing between latency-focused read operation and ban...
- Patent number 11,036,412
- Issue date Jun 15, 2021
- Intel Corporation
- Sahar Khalili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast page fault handling process implemented on persistent memory
- Patent number 10,949,356
- Issue date Mar 16, 2021
- Intel Corporation
- James A. Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi level system memory having different caching structures and m...
- Patent number 10,915,453
- Issue date Feb 9, 2021
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory with scrubber logic
- Patent number 10,678,706
- Issue date Jun 9, 2020
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved cache controllers with shared metadata and related devi...
- Patent number 10,657,058
- Issue date May 19, 2020
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent accesses of asymmetrical memory sources
- Patent number 10,558,570
- Issue date Feb 11, 2020
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating system transparent system memory abandonment
- Patent number 10,304,418
- Issue date May 28, 2019
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse superline removal
- Patent number 10,241,916
- Issue date Mar 26, 2019
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 10,210,925
- Issue date Feb 19, 2019
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for multi-level system memory with coherency unit
- Patent number 10,204,047
- Issue date Feb 12, 2019
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using data pattern to mark cache lines as invalid
- Patent number 10,176,099
- Issue date Jan 8, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 9,865,326
- Issue date Jan 9, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing sectored cache
- Patent number 9,767,041
- Issue date Sep 19, 2017
- Intel Corporation
- Aravindh V. Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 9,747,971
- Issue date Aug 29, 2017
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid exclusive multi-level memory architecture with memory manage...
- Patent number 9,734,079
- Issue date Aug 15, 2017
- Intel Corporation
- Dannie G. Feekes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetric set combined cache
- Patent number 9,582,430
- Issue date Feb 28, 2017
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system and apparatus including logic to manage multiple mem...
- Patent number 9,424,198
- Issue date Aug 23, 2016
- Intel Corporation
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective prefetching for a sectored cache
- Patent number 9,418,013
- Issue date Aug 16, 2016
- Intel Corporation
- Aravindh V. Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Throttling support for row-hammer counters
- Patent number 9,251,885
- Issue date Feb 2, 2016
- Intel Corporation
- Zvika Greenfield
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh command
- Patent number 9,236,110
- Issue date Jan 12, 2016
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh command
- Patent number 9,117,544
- Issue date Aug 25, 2015
- Intel Corporation
- Kuljit Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for memory encryption with integrity check and...
- Patent number 9,076,019
- Issue date Jul 7, 2015
- Intel Corporation
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for providing a memory refresh
- Patent number 9,030,903
- Issue date May 12, 2015
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Training for command/address/control/clock delays under uncertain i...
- Patent number 9,026,725
- Issue date May 5, 2015
- Intel Corporation
- Alexey Kostinsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory subsystem command bus stress testing
- Patent number 9,009,540
- Issue date Apr 14, 2015
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic priority control based on latency tolerance
- Patent number 8,959,266
- Issue date Feb 17, 2015
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Robust memory link testing using memory controller
- Patent number 8,868,992
- Issue date Oct 21, 2014
- Intel Corporation
- Bryan L. Spry
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...
- Publication number 20210056030
- Publication date Feb 25, 2021
- Intel Corporation
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
- Publication number 20200226066
- Publication date Jul 16, 2020
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY CHANGING BETWEEN LATENCY-FOCUSED READ OPERATION AND BAN...
- Publication number 20200034061
- Publication date Jan 30, 2020
- Intel Corporation
- Sahar KHALILI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST PAGE FAULT HANDLING PROCESS IMPLEMENTED ON PERSISTENT MEMORY
- Publication number 20190303300
- Publication date Oct 3, 2019
- Intel Corporation
- James A. BOYD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG CACHE ADAPTIVE POWER GATING
- Publication number 20190102314
- Publication date Apr 4, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...
- Publication number 20190095331
- Publication date Mar 28, 2019
- Intel Corporation
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY WITH SCRUBBER LOGIC
- Publication number 20190050346
- Publication date Feb 14, 2019
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVI...
- Publication number 20190004953
- Publication date Jan 3, 2019
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE SUPERLINE REMOVAL
- Publication number 20180285271
- Publication date Oct 4, 2018
- Intel Corporation
- Zvika GREENFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND M...
- Publication number 20180189192
- Publication date Jul 5, 2018
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20180174639
- Publication date Jun 21, 2018
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT
- Publication number 20180089096
- Publication date Mar 29, 2018
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING DATA PATTERN TO MARK CACHE LINES AS INVALID
- Publication number 20180011790
- Publication date Jan 11, 2018
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVI...
- Publication number 20170329711
- Publication date Nov 16, 2017
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL MEMORY MANAGEMENT
- Publication number 20170300415
- Publication date Oct 19, 2017
- Intel Corporation
- Nadav BONEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FOR MULTI-LEVEL SYSTEM MEMORY HAVING SECTORED CACHE
- Publication number 20170091099
- Publication date Mar 30, 2017
- ZVIKA GREENFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20170076779
- Publication date Mar 16, 2017
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING SECTORED CACHE
- Publication number 20160350237
- Publication date Dec 1, 2016
- Intel Corporation
- Aravindh V. Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller For Multi-Level System Memory With Coherency Unit
- Publication number 20160283389
- Publication date Sep 29, 2016
- ISRAEL DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC SET COMBINED CACHE
- Publication number 20160283392
- Publication date Sep 29, 2016
- Intel Corporation
- Zvika Greenfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20160225433
- Publication date Aug 4, 2016
- Intel Corporation
- Kuljit S Bains
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE PREFETCHING FOR A SECTORED CACHE
- Publication number 20150378919
- Publication date Dec 31, 2015
- ARAVINDH V. ANANTARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE
- Publication number 20150039790
- Publication date Feb 5, 2015
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID MULTI-LEVEL MEMORY ARCHITECTURE
- Publication number 20150006805
- Publication date Jan 1, 2015
- DANNIE G. FEEKES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND...
- Publication number 20140223197
- Publication date Aug 7, 2014
- Shay Gueron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING FOR MAPPING SWIZZLED DATA TO COMMAND/ADDRESS SIGNALS
- Publication number 20140189224
- Publication date Jul 3, 2014
- ALEXEY KOSTINSKY
- G11 - INFORMATION STORAGE
Information Patent Application
Unified Exclusive Memory
- Publication number 20140156935
- Publication date Jun 5, 2014
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING
- Publication number 20140157055
- Publication date Jun 5, 2014
- CHRISTOPHER P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH
- Publication number 20140089576
- Publication date Mar 27, 2014
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR DETERMINING A COUNT OF ACCESSES TO...
- Publication number 20140085995
- Publication date Mar 27, 2014
- Zvika Greenfield
- G11 - INFORMATION STORAGE

ZVIKA GREENFIELD

Person

Patents Grantslast 30 patents

Multi-level system memory with near memory capable of storing compr...

Dynamically changing between latency-focused read operation and ban...

Fast page fault handling process implemented on persistent memory

Multi level system memory having different caching structures and m...

Cache memory with scrubber logic

Interleaved cache controllers with shared metadata and related devi...

Concurrent accesses of asymmetrical memory sources

Operating system transparent system memory abandonment

Sparse superline removal

Row hammer refresh command

Memory controller for multi-level system memory with coherency unit

Using data pattern to mark cache lines as invalid

Row hammer refresh command

Managing sectored cache

Row hammer refresh command

Hybrid exclusive multi-level memory architecture with memory manage...

Asymmetric set combined cache

Method, system and apparatus including logic to manage multiple mem...

Selective prefetching for a sectored cache

Throttling support for row-hammer counters

Row hammer refresh command

Row hammer refresh command

Method and apparatus for memory encryption with integrity check and...

Method, apparatus and system for providing a memory refresh

Training for command/address/control/clock delays under uncertain i...

Memory subsystem command bus stress testing

Dynamic priority control based on latency tolerance

Robust memory link testing using memory controller

Patents Applicationslast 30 patents

MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...

APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY

DYNAMICALLY CHANGING BETWEEN LATENCY-FOCUSED READ OPERATION AND BAN...

FAST PAGE FAULT HANDLING PROCESS IMPLEMENTED ON PERSISTENT MEMORY

TAG CACHE ADAPTIVE POWER GATING

MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...

CACHE MEMORY WITH SCRUBBER LOGIC

INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVI...

SPARSE SUPERLINE REMOVAL

MULTI LEVEL SYSTEM MEMORY HAVING DIFFERENT CACHING STRUCTURES AND M...

ROW HAMMER REFRESH COMMAND

OPERATING SYSTEM TRANSPARENT SYSTEM MEMORY ABANDONMENT

USING DATA PATTERN TO MARK CACHE LINES AS INVALID

INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVI...

ASYMMETRICAL MEMORY MANAGEMENT

MEMORY CONTROLLER FOR MULTI-LEVEL SYSTEM MEMORY HAVING SECTORED CACHE

ROW HAMMER REFRESH COMMAND

MANAGING SECTORED CACHE

Memory Controller For Multi-Level System Memory With Coherency Unit

ASYMMETRIC SET COMBINED CACHE

ROW HAMMER REFRESH COMMAND

SELECTIVE PREFETCHING FOR A SECTORED CACHE

DYNAMIC PRIORITY CONTROL BASED ON LATENCY TOLERANCE

HYBRID MULTI-LEVEL MEMORY ARCHITECTURE

METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND...

TRAINING FOR MAPPING SWIZZLED DATA TO COMMAND/ADDRESS SIGNALS

Unified Exclusive Memory

MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING

METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH

METHOD, APPARATUS AND SYSTEM FOR DETERMINING A COUNT OF ACCESSES TO...