2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead

Industry

CPC
G06F2207/5063

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F2207/50632-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead

Industries

Patents Grantslast 30 patents

Information Patent Grant
Concurrent multi-bit adder
- Patent number 11,681,497
- Issue date Jun 20, 2023
- GSI Technology Inc.
- Moshe Lazer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuitry for very large integers
- Patent number 11,662,979
- Issue date May 30, 2023
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix network-directed addition
- Patent number 11,334,318
- Issue date May 17, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA logic cell with improved support for counters
- Patent number 10,936,286
- Issue date Mar 2, 2021
- MICROSEMI SOC CORP.
- Jonathan W. Greene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuitry for very large integers
- Patent number 10,873,332
- Issue date Dec 22, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent multi-bit adder
- Patent number 10,824,394
- Issue date Nov 3, 2020
- GSI Technology Inc.
- Moshe Lazer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent multi-bit adder
- Patent number 10,402,165
- Issue date Sep 3, 2019
- GSI Technology Inc.
- Moshe Lazer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient variable power adder and methods of use thereof
- Patent number 10,223,071
- Issue date Mar 5, 2019
- QUALCOMM Incorporated
- Hari Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-pass parallel prefix scan with dynamic look back
- Patent number 9,928,033
- Issue date Mar 27, 2018
- NVIDIA Corporation
- Duane Merrill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a fast 3x multiplicand term for radix-8 booth multiplica...
- Patent number 9,146,707
- Issue date Sep 29, 2015
- International Business Machines Corporation
- Deepak K. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for performing a scan...
- Patent number 8,661,226
- Issue date Feb 25, 2014
- NVIDIA Corporation
- Michael J. Garland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cyclic segmented prefix circuits for mesh networks
- Patent number 7,933,940
- Issue date Apr 26, 2011
- International Business Machines Corporation
- Matteo Frigo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Work-efficient parallel prefix sum algorithm for graphics processin...
- Patent number 7,725,518
- Issue date May 25, 2010
- NVIDIA Corporation
- Scott M. Le Grand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed parallel-prefix modulo 2n-1 adders
- Patent number 7,155,473
- Issue date Dec 26, 2006
- UTStarcom, Inc.
- Lampros Kalampoukas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel prefix networks that make tradeoffs between logic levels,...
- Patent number 7,152,089
- Issue date Dec 19, 2006
- Sun Microsystems, Inc.
- David L. Harris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder increment circuit
- Patent number 7,139,789
- Issue date Nov 21, 2006
- Broadcom Corporation
- Richard J. Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry foreknowledge adder
- Patent number 7,111,034
- Issue date Sep 19, 2006
- Oki Electric Industry Co., Ltd.
- Shinichi Ozawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder with improved overflow flag generation
- Patent number 6,912,560
- Issue date Jun 28, 2005
- Agere Systems, INC
- Alexander Goldovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for speculative addition using a limited carry
- Patent number 6,631,393
- Issue date Oct 7, 2003
- Intel Corporation
- Xia Dai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cycle segmented prefix circuits
- Patent number 6,609,189
- Issue date Aug 19, 2003
- Yale University
- Bradley C. Kuszmaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise-tolerant digital adder circuit and method
- Patent number 6,571,269
- Issue date May 27, 2003
- Intel Corporation
- Ram K. Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix sums and an application thereof
- Patent number 6,542,918
- Issue date Apr 1, 2003
- Ramot at Tel Aviv University Ltd.
- Uzi Vishkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix tree adder with efficient sum generation
- Patent number 6,539,413
- Issue date Mar 25, 2003
- Agere Systems Inc.
- Alexander Goldovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix tree adder with efficient carry generation
- Patent number 6,529,931
- Issue date Mar 4, 2003
- Agere Systems Inc.
- Matthew Besz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Designing addition circuits
- Patent number 6,519,622
- Issue date Feb 11, 2003
- STMicroelectronics Limited
- Simon Knowles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incrementer/decrementer having a reduced fanout architecture
- Patent number 6,516,335
- Issue date Feb 4, 2003
- Agilent Technologies, Inc.
- Robert J Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel adder with independent odd and even sum bit generation cells
- Patent number 6,134,576
- Issue date Oct 17, 2000
- Mentor Graphics Corporation
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of operation of arithmetic and logic unit, storage medium, a...
- Patent number 6,028,987
- Issue date Feb 22, 2000
- Sony Corporation
- Koji Hirairi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing circuits for wave pipelining
- Patent number 5,796,624
- Issue date Aug 18, 1998
- Research Foundation of State University of New York
- Ramalingam Sridhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-performance differential cascode voltage switch with pass gate...
- Patent number 5,777,491
- Issue date Jul 7, 1998
- International Business Machines Corporation
- Wei Hwang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONCURRENT MULTI-BIT ADDER
- Publication number 20230333815
- Publication date Oct 19, 2023
- GSI Technology Inc.
- Moshe LAZER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER CIRCUITRY FOR VERY LARGE INTEGERS
- Publication number 20210075425
- Publication date Mar 11, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS
- Publication number 20200150925
- Publication date May 14, 2020
- Microsemi SoC Corp.
- Jonathan W. Greene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT MULTI-BIT ADDER
- Publication number 20190384573
- Publication date Dec 19, 2019
- GSI Technology Inc.
- Moshe LAZER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE-PASS PARALLEL PREFIX SCAN WITH DYNAMIC LOOK BACK
- Publication number 20140380317
- Publication date Dec 25, 2014
- NVIDIA Corporation
- Duane MERRILL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION
- Publication number 20140358979
- Publication date Dec 4, 2014
- Deepak K. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-BIT ADDER AND CORRESPONDING ADDITION METHOD
- Publication number 20090204659
- Publication date Aug 13, 2009
- S.A.R..L. DANIEL TRONO
- Daniel Torno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING A SCAN...
- Publication number 20090132878
- Publication date May 21, 2009
- Michael J. Garland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Universal execution unit
- Publication number 20080281897
- Publication date Nov 13, 2008
- Daaven S. Messinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cyclic segmented prefix circuits for mesh networks
- Publication number 20070260663
- Publication date Nov 8, 2007
- Matteo Frigo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient circuits for out-of-order microprocessors
- Publication number 20060015547
- Publication date Jan 19, 2006
- Yale University
- Bradley C. Kuszmaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel prefix networks that make tradeoffs between logic levels,...
- Publication number 20040225706
- Publication date Nov 11, 2004
- David L. Harris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power adder
- Publication number 20040220993
- Publication date Nov 4, 2004
- Intel Corporation
- Sanu K. Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-speed parallel-prefix modulo 2n-1 adders
- Publication number 20040128339
- Publication date Jul 1, 2004
- Lampros Kalampoukas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient circuits for out-of-order microprocessors
- Publication number 20040034678
- Publication date Feb 19, 2004
- Yale University
- Bradley C. Kuszmaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Carry foreknowledge adder
- Publication number 20030225810
- Publication date Dec 4, 2003
- Shinichi Ozawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Addition circuits
- Publication number 20030158882
- Publication date Aug 21, 2003
- STMicroelectronics Limited
- Simon Knowles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CARRY LOOKAHEAD ADDER HAVING A REDUCED FANOUT ARCHITECTURE
- Publication number 20030069914
- Publication date Apr 10, 2003
- AGILENT TECHNOLOGIES
- GREGORY S. DIX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder increment circuit
- Publication number 20030061253
- Publication date Mar 27, 2003
- Broadcom Corporation
- Richard J. Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adder with improved overflow flag generation
- Publication number 20020103842
- Publication date Aug 1, 2002
- Alexander Goldovsky
- G06 - COMPUTING CALCULATING COUNTING

2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Concurrent multi-bit adder

Adder circuitry for very large integers

Prefix network-directed addition

FPGA logic cell with improved support for counters

Adder circuitry for very large integers

Concurrent multi-bit adder

Concurrent multi-bit adder

Energy-efficient variable power adder and methods of use thereof

Single-pass parallel prefix scan with dynamic look back

Generating a fast 3x multiplicand term for radix-8 booth multiplica...

System, method, and computer program product for performing a scan...

Cyclic segmented prefix circuits for mesh networks

Work-efficient parallel prefix sum algorithm for graphics processin...

High-speed parallel-prefix modulo 2n-1 adders

Parallel prefix networks that make tradeoffs between logic levels,...

Adder increment circuit

Carry foreknowledge adder

Adder with improved overflow flag generation

Method and apparatus for speculative addition using a limited carry

Cycle segmented prefix circuits

Noise-tolerant digital adder circuit and method

Prefix sums and an application thereof

Prefix tree adder with efficient sum generation

Prefix tree adder with efficient carry generation

Designing addition circuits

Incrementer/decrementer having a reduced fanout architecture

Parallel adder with independent odd and even sum bit generation cells

Method of operation of arithmetic and logic unit, storage medium, a...

Method and apparatus for designing circuits for wave pipelining

High-performance differential cascode voltage switch with pass gate...

Patents Applicationslast 30 patents

CONCURRENT MULTI-BIT ADDER

ADDER CIRCUITRY FOR VERY LARGE INTEGERS

FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS

CONCURRENT MULTI-BIT ADDER

SINGLE-PASS PARALLEL PREFIX SCAN WITH DYNAMIC LOOK BACK

GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION

N-BIT ADDER AND CORRESPONDING ADDITION METHOD

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING A SCAN...

Universal execution unit

Cyclic segmented prefix circuits for mesh networks

Efficient circuits for out-of-order microprocessors

Parallel prefix networks that make tradeoffs between logic levels,...

Low power adder

High-speed parallel-prefix modulo 2n-1 adders

Efficient circuits for out-of-order microprocessors

Carry foreknowledge adder

Addition circuits

CARRY LOOKAHEAD ADDER HAVING A REDUCED FANOUT ARCHITECTURE

Adder increment circuit

Adder with improved overflow flag generation