Acceleration testing

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CPC
G11C29/06

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/06Acceleration testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for checking the results of characterized mem...
- Patent number 11,847,183
- Issue date Dec 19, 2023
- Micron Technology, Inc.
- Jonathan D. Harms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for trimming analog temperature sensors
- Patent number 11,668,612
- Issue date Jun 6, 2023
- SanDisk Technologies LLC
- Venkata Nittala
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for checking the results of characterized mem...
- Patent number 11,256,778
- Issue date Feb 22, 2022
- Micron Technology, Inc.
- Jonathan D. Harms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substitute redundant memory
- Patent number 11,119,857
- Issue date Sep 14, 2021
- MoSys, Inc.
- Dipak K Sikdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 11,094,391
- Issue date Aug 17, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient scrambling and encoding for copyback procedures in a memo...
- Patent number 10,923,211
- Issue date Feb 16, 2021
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully testible OTP memory
- Patent number 10,923,204
- Issue date Feb 16, 2021
- Attopsemi Technology Co., Ltd.
- Shine C. Chung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with controller and memory chips, where controller ca...
- Patent number 10,892,030
- Issue date Jan 12, 2021
- TOSHIBA MEMORY CORPORATION
- Kenichi Arai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error counters on a memory device
- Patent number 10,891,185
- Issue date Jan 12, 2021
- Hewlett Packard Enterprise Development LP
- Lidia Warnes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solid-state disk manufacturing self test
- Patent number 10,803,970
- Issue date Oct 13, 2020
- Seagate Technology LLC
- Karl David Schuh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining highest performance of DDR5 channel with marginal signa...
- Patent number 10,685,736
- Issue date Jun 16, 2020
- Dell Products, L.P.
- Stuart A. Berke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancing memory yield and performance through utilizing nanowire s...
- Patent number 10,679,719
- Issue date Jun 9, 2020
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic timing and reliability repair for nanowire circuits
- Patent number 10,665,320
- Issue date May 26, 2020
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of testing semiconductor device and method of manufacturing...
- Patent number 10,620,258
- Issue date Apr 14, 2020
- Samsung Electronics Co., Ltd.
- Jae-hoon Kim
- G01 - MEASURING TESTING
Information Patent Grant
Detecting random telegraph noise defects in memory
- Patent number 10,510,431
- Issue date Dec 17, 2019
- QUALCOMM Incorporated
- Sneha Revankar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory subsystem I/O performance based on in-system empirical testing
- Patent number 10,446,222
- Issue date Oct 15, 2019
- Intel Corporation
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory diagnosis apparatus and memory diagnosis program
- Patent number 10,438,679
- Issue date Oct 8, 2019
- Mitsubishi Electric Corporation
- Ryoya Ichioka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device and method of read/write operation for...
- Patent number 10,388,348
- Issue date Aug 20, 2019
- TOSHIBA MEMORY CORPORATION
- Naoki Shimizu
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic timing and reliability repair for nanowire circuits
- Patent number 10,388,397
- Issue date Aug 20, 2019
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit with improved read and write access
- Patent number 10,387,047
- Issue date Aug 20, 2019
- Etron Technology, Inc.
- Chun Shiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus including a command controller
- Patent number 10,388,398
- Issue date Aug 20, 2019
- Samsung Electronics Co., Ltd.
- Jeong-Hwa Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhancing memory yield and performance through utilizing nanowire s...
- Patent number 10,381,100
- Issue date Aug 13, 2019
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of manufacturing semiconductor device and semiconductor device
- Patent number 10,381,279
- Issue date Aug 13, 2019
- Renesas Electronics Corporation
- Akira Yajima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overheat protection circuit and method in an accelerated aging test...
- Patent number 10,371,745
- Issue date Aug 6, 2019
- Micron Technology, Inc.
- Ronny Schneider
- G01 - MEASURING TESTING
Information Patent Grant
SRAM margin recovery during burn-in
- Patent number 10,373,678
- Issue date Aug 6, 2019
- International Business Machines Corporation
- William V. Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and system relating to the reduction of test t...
- Patent number 10,276,257
- Issue date Apr 30, 2019
- SK hynix Inc.
- Min Sik Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DRAM adjacent row disturb mitigation
- Patent number 10,262,717
- Issue date Apr 16, 2019
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit capable of being quickly written in data
- Patent number 10,255,965
- Issue date Apr 9, 2019
- Etron Technology, Inc.
- Chun Shiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary scan testing a storage device via system management bus in...
- Patent number 10,162,006
- Issue date Dec 25, 2018
- Western Digital Technologies, Inc.
- Gobinathan Athimolom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and electronic device
- Patent number 10,115,741
- Issue date Oct 30, 2018
- Semiconductor Energy Laboratory Co., Ltd.
- Shinpei Matsuda
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR CHECKING THE RESULTS OF CHARACTERIZED MEM...
- Publication number 20220171826
- Publication date Jun 2, 2022
- Micron Technology, Inc.
- Jonathan D. Harms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR CHECKING THE RESULTS OF CHARACTERIZED MEM...
- Publication number 20200264689
- Publication date Aug 20, 2020
- Micron Technology, Inc.
- Jonathan D. Harms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING HIGHEST PERFORMANCE OF DDR5 CHANNEL WITH MARGINAL SIGNA...
- Publication number 20200035321
- Publication date Jan 30, 2020
- DELL PRODUCTS, L.P.
- STUART A. BERKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhancing Memory Yield and Performance Through Utilizing Nanowire S...
- Publication number 20190355437
- Publication date Nov 21, 2019
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic Timing and Reliability Repair for Nanowire Circuits
- Publication number 20190333600
- Publication date Oct 31, 2019
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BURN-IN TEST DEVICE AND TEST METHOD USING INTERPOSER
- Publication number 20190170814
- Publication date Jun 6, 2019
- Samsung Electronics Co., Ltd.
- Joosung YUN
- G11 - INFORMATION STORAGE
Information Patent Application
DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
- Publication number 20180225234
- Publication date Aug 9, 2018
- SK HYNIX INC.
- Jeen PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
- Publication number 20180068910
- Publication date Mar 8, 2018
- RENESAS ELECTRONICS CORPORATION
- Akira YAJIMA
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS INTERFACE
- Publication number 20170337987
- Publication date Nov 23, 2017
- Western Digital Technologies, Inc.
- Gurjit CHADHA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND...
- Publication number 20140317460
- Publication date Oct 23, 2014
- MoSys, Inc.
- Bendik Kleveland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE
- Publication number 20140241040
- Publication date Aug 28, 2014
- SK HYNIX INC.
- Hoe-Gwon Jeong
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
- Publication number 20140233339
- Publication date Aug 21, 2014
- SPANSION LLC
- Amichai GIVANT
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC HARD ERROR DETECTION
- Publication number 20140229776
- Publication date Aug 14, 2014
- International Business Machines Corporation
- Pradip Bose
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC HARD ERROR DETECTION
- Publication number 20140229784
- Publication date Aug 14, 2014
- International Business Machines Corporation
- Pradip Bose
- G01 - MEASURING TESTING
Information Patent Application
MEMORY SUBSYSTEM I/O PERFORMANCE BASED ON IN-SYSTEM EMPIRICAL TESTING
- Publication number 20140229666
- Publication date Aug 14, 2014
- THEODORE Z. SCHOENBORN
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Device Performing Stress Test
- Publication number 20140211582
- Publication date Jul 31, 2014
- Yoshiro Riho
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUBSYSTEM PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
- Publication number 20140189433
- Publication date Jul 3, 2014
- THEODORE Z. SCHOENBORN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUBSYSTEM DATA BUS STRESS TESTING
- Publication number 20140157053
- Publication date Jun 5, 2014
- CHRISTOPHER P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING
- Publication number 20140157055
- Publication date Jun 5, 2014
- CHRISTOPHER P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-GOING RELIABILITY MONITORING OF INTEGRATED CIRCUIT CHIPS IN THE...
- Publication number 20140088947
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Theodoros E. Anemikos
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFIC...
- Publication number 20140070212
- Publication date Mar 13, 2014
- RENESAS ELECTRONICS CORPORATION
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE FIRMWARE AND MANUFACTURING SOFTWARE
- Publication number 20140059278
- Publication date Feb 27, 2014
- LSI Corporation
- Karl David SCHUH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NO-TOUCH STRESS TESTING OF MEMORY I/O INTERFACES
- Publication number 20140006864
- Publication date Jan 2, 2014
- Intel Corporation
- Sankaran M. Menon
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR PRECONDITIONING THIN FILM STORAGE ARRAY FOR DATA RETENTION
- Publication number 20130343112
- Publication date Dec 26, 2013
- HORACIO P. GASQUET
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST...
- Publication number 20130332802
- Publication date Dec 12, 2013
- Kabushiki Kaisha Toshiba
- Daisuke HASHIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
STRESS-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A...
- Publication number 20130326285
- Publication date Dec 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Richard K. Eguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20130308401
- Publication date Nov 21, 2013
- SK HYNIX INC.
- Sun Suk YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE
- Publication number 20130301330
- Publication date Nov 14, 2013
- Elpida Memory, Inc.
- Yasuhiro MATSUMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
ARCHITECTURE, SYSTEM AND METHOD FOR TESTING RESISTIVE TYPE MEMORY
- Publication number 20130301335
- Publication date Nov 14, 2013
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES
- Publication number 20130293250
- Publication date Nov 7, 2013
- GLOBALFOUNDRIES INC.
- William McMahon
- G01 - MEASURING TESTING

Acceleration testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for checking the results of characterized mem...

Apparatus, system, and method for trimming analog temperature sensors

Methods and apparatus for checking the results of characterized mem...

Substitute redundant memory

List insertion in test segments with non-naturally aligned data bou...

Efficient scrambling and encoding for copyback procedures in a memo...

Fully testible OTP memory

Memory system with controller and memory chips, where controller ca...

Error counters on a memory device

Solid-state disk manufacturing self test

Maintaining highest performance of DDR5 channel with marginal signa...

Enhancing memory yield and performance through utilizing nanowire s...

Logic timing and reliability repair for nanowire circuits

Method of testing semiconductor device and method of manufacturing...

Detecting random telegraph noise defects in memory

Memory subsystem I/O performance based on in-system empirical testing

Memory diagnosis apparatus and memory diagnosis program

Semiconductor memory device and method of read/write operation for...

Logic timing and reliability repair for nanowire circuits

Memory circuit with improved read and write access

Memory apparatus including a command controller

Enhancing memory yield and performance through utilizing nanowire s...

Method of manufacturing semiconductor device and semiconductor device

Overheat protection circuit and method in an accelerated aging test...

SRAM margin recovery during burn-in

Semiconductor device and system relating to the reduction of test t...

DRAM adjacent row disturb mitigation

Memory circuit capable of being quickly written in data

Boundary scan testing a storage device via system management bus in...

Semiconductor device and electronic device

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR CHECKING THE RESULTS OF CHARACTERIZED MEM...

METHODS AND APPARATUS FOR CHECKING THE RESULTS OF CHARACTERIZED MEM...

MAINTAINING HIGHEST PERFORMANCE OF DDR5 CHANNEL WITH MARGINAL SIGNA...

Enhancing Memory Yield and Performance Through Utilizing Nanowire S...

Logic Timing and Reliability Repair for Nanowire Circuits

BURN-IN TEST DEVICE AND TEST METHOD USING INTERPOSER

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

SELF-TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS INTERFACE

MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND...

ELECTRONIC DEVICE

APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS

DYNAMIC HARD ERROR DETECTION

DYNAMIC HARD ERROR DETECTION

MEMORY SUBSYSTEM I/O PERFORMANCE BASED ON IN-SYSTEM EMPIRICAL TESTING

Semiconductor Device Performing Stress Test

MEMORY SUBSYSTEM PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION

MEMORY SUBSYSTEM DATA BUS STRESS TESTING

MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING

ON-GOING RELIABILITY MONITORING OF INTEGRATED CIRCUIT CHIPS IN THE...

SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFIC...

STORAGE DEVICE FIRMWARE AND MANUFACTURING SOFTWARE

NO-TOUCH STRESS TESTING OF MEMORY I/O INTERFACES

METHOD FOR PRECONDITIONING THIN FILM STORAGE ARRAY FOR DATA RETENTION

SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST...

STRESS-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A...

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

ARCHITECTURE, SYSTEM AND METHOD FOR TESTING RESISTIVE TYPE MEMORY

INTEGRATED CIRCUIT WITH STRESS GENERATOR FOR STRESSING TEST DEVICES