Additive or subtractive mixing of two pulse rates into one

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/605Additive or subtractive mixing of two pulse rates into one

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Patents Grantslast 30 patents

Information Patent Grant
System and method for pipelined time-domain computing using time-do...
- Patent number 11,467,831
- Issue date Oct 11, 2022
- Northwestern University
- Jie Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC transmitter digital phase domain calculator with atomic computat...
- Patent number 10,911,056
- Issue date Feb 2, 2021
- Texas Instruments Incorporated
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed based arithmetic units
- Patent number 10,608,660
- Issue date Mar 31, 2020
- University of Florida Research Foundation, Inc.
- Gabriel Nallathambi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software reconfigurable digital phase lock loop architecture
- Patent number 10,447,285
- Issue date Oct 15, 2019
- Roman Staszewki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable calculation unit with atomic computation units and c...
- Patent number 10,122,371
- Issue date Nov 6, 2018
- Texas Instruments Incorporated
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase domain calculator clock, ALU, memory, register file, sequence...
- Patent number 9,853,649
- Issue date Dec 26, 2017
- Texas Instruments Incorporated
- Roman Staszewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software reconfigurable digital phase lock loop architecture
- Patent number 9,473,155
- Issue date Oct 18, 2016
- Texas Instruments Incorporated
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
ASIP with reconfigurable circuitry implementing atomic operations o...
- Patent number 9,116,769
- Issue date Aug 25, 2015
- Texas Instruments Incorporated
- Roman Staszewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software reconfigurable digital phase lock loop architecture
- Patent number 8,321,489
- Issue date Nov 27, 2012
- National Semiconductor Corporation
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase lock loop circuit having a broad loop band and small step fre...
- Patent number 5,831,481
- Issue date Nov 3, 1998
- NEC Corporation
- Toshiyuki Oga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop circuitry including a multiple frequency output v...
- Patent number 5,786,732
- Issue date Jul 28, 1998
- VLSI Technology, Inc.
- Edward T. Nielson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop having voltage controlled oscillator utilizing co...
- Patent number 5,614,868
- Issue date Mar 25, 1997
- VLSI Technology, Inc.
- Edward T. Nielson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CVSD digital adder
- Patent number 4,091,452
- Issue date May 23, 1978
- International Telephone and Telegraph Corporation
- Charles Robert Maggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for combining pulse trains
- Patent number 4,001,701
- Issue date Jan 4, 1977
- Combustion Engineering, Inc.
- John B. Rosso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3851255
- Patent number 3,851,255
- Issue date Nov 26, 1974
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3725688
- Patent number 3,725,688
- Issue date Apr 3, 1973
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3644721
- Patent number 3,644,721
- Issue date Feb 22, 1972
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3593161
- Patent number 3,593,161
- Issue date Jul 13, 1971
- B60 - VEHICLES IN GENERAL
Information Patent Grant
3568022
- Patent number 3,568,022
- Issue date Mar 2, 1971
- B60 - VEHICLES IN GENERAL
Information Patent Grant
3537002
- Patent number 3,537,002
- Issue date Oct 27, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3534261
- Patent number 3,534,261
- Issue date Oct 13, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3514705
- Patent number 3,514,705
- Issue date May 26, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3440645
- Patent number 3,440,645
- Issue date Apr 22, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3427442
- Patent number 3,427,442
- Issue date Feb 11, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3040187
- Patent number 3,040,187
- Issue date Jun 19, 1962
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3004249
- Patent number 3,004,249
- Issue date Oct 10, 1961
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2795695
- Patent number 2,795,695
- Issue date Jun 11, 1957
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR PIPELINED TIME-DOMAIN COMPUTING USING TIME-DO...
- Publication number 20220019434
- Publication date Jan 20, 2022
- Northwestern University
- Jie Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20200007134
- Publication date Jan 2, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20190020349
- Publication date Jan 17, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSED BASED ARITHMETIC UNITS
- Publication number 20180269894
- Publication date Sep 20, 2018
- University of Florida Research Foundation, Inc.
- GABRIEL NALLATHAMBI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20180083644
- Publication date Mar 22, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20130080495
- Publication date Mar 28, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Software reconfigurable digital phase lock loop architecture
- Publication number 20080072025
- Publication date Mar 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING

Additive or subtractive mixing of two pulse rates into one

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System and method for pipelined time-domain computing using time-do...

IC transmitter digital phase domain calculator with atomic computat...

Pulsed based arithmetic units

Software reconfigurable digital phase lock loop architecture

Reconfigurable calculation unit with atomic computation units and c...

Phase domain calculator clock, ALU, memory, register file, sequence...

Software reconfigurable digital phase lock loop architecture

ASIP with reconfigurable circuitry implementing atomic operations o...

Software reconfigurable digital phase lock loop architecture

Phase lock loop circuit having a broad loop band and small step fre...

Phase locked loop circuitry including a multiple frequency output v...

Phase locked loop having voltage controlled oscillator utilizing co...

CVSD digital adder

Circuit for combining pulse trains

3851255

3725688

3644721

3593161

3568022

3537002

3534261

3514705

3440645

3427442

3040187

3004249

2795695

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR PIPELINED TIME-DOMAIN COMPUTING USING TIME-DO...

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

PULSED BASED ARITHMETIC UNITS

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

Software reconfigurable digital phase lock loop architecture