Some microprocessor designs have reached a bottleneck on further improvements related to speed, e.g., which can cause delay in the transmission of data through the microprocessor. The delay can occur when a system's bandwidth cannot support the amount of information being relayed at the speed it is processed. Bottlenecks can affect microprocessor performance by slowing down the flow of information between the computer processing unit (CPU) and memory.
The disclosure is better understood with reference to the following drawings and description.
The elements in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the disclosure. Moreover, in the figures, like-referenced numerals may designate to corresponding parts throughout the different views.
The system and/or methods h can improve energy efficiency of time domain signal processing. One example of energy efficient time domain signal processing is described in commonly assigned Pub. Patent Application No. 2017/0194982, entitled, “System and Method for Energy Efficient Time Domain Signal Processing,” the entire contents of which are incorporated by reference herein. In some existing designs, a lack of storage unit prevents time-domain pipeline structure computing.
The disclosure describes systems and/or methods using new time-domain flip-flops (TFF) to build pipelined structure. The enabled pipeline structure may enhance throughputs of the design. A simple logic operation in the pipeline structure is also described, such as Min, ABS operations in time-domain that carry out a dynamic time warping algorithm using time-domain circuits hardware constructions. Examples of a hardware implemented method using circuit techniques carry out dynamic time warping algorithm for time series analysis finds applications in voice recognition, motion detection, DNA sequencing, etc.
Dynamic time warping (DTW) is a variant of the dynamic programming algorithm, is used for time signal classifications. The strong capability of distance measurement for variable speed temporal sequences makes DTW a prevalent method for time series classifications in broad applications such as, ECG diagnosis, DNA sequencing, etc. Several efforts have been proposed in accelerating the operation including a recent demonstration of race-logic. However, the demonstration is confined to a single-bit operation, not scalable with variable sequence length and has low throughput due to its non-pipelined operation. To overcome those challenges, the systems and/or methods describe a DTW engine for time series classifications using time-domain computing. A pipelined operation uses time flip-flop (TFF) which can lead to an order of magnitude improvements in throughput and a scalable processing capability of time sequence. Compared with recent time-domain designs which suffer from low bit precision and lack of memory element, a pipeline structure is implemented all in time-domain with up to a 10 bit resolution.
A “warping path” 120 is produced in order to align the two signals Ai and Bj in time t as marked in graph 100 of
During readout phase, the stored pulse is sent out from the output pin 615 of the ring 610 with pulse width equivalent to the stored values. When the ring is filled, a carry signal rises and the ring will rotate back with reminder values stored inside. The “rotation” operation provides a scalable operation into multi-bit groups. Different from conventional D-flip-flops 510, each TFF 650 can process multi-bit signals. In on example, each TFF 650 can store a 6-bit time domain signal and two TFFs 810 (see
At step 1606, the process performs the time-domain pulse comparison operation by taking an absolute difference operation on the pair of time sample signals Ai and Bj to obtain the resultant time pulse T(Di,j), wherein T(Di,j)=ABS (Ai−Bj) and the resultant time pulse T(Di,j) is stored in the TFF for carrying out more time-domain pulses comparison operation with neighboring nodes in a next clock cycle to generate new resultant time pulses T(Di,j), until all nodes Di,j within an i×j dimension matrix between the time sequences A and B are determined.
At step 1608, the time-domain pulses comparison operation may additionally take a minimum value operation (MIN) of three ancestor nodes (Di-1,j, Di-1,j-1, Di,j-1), wherein T(Di,j)=MIN (Di-1,j, Di-1,j-1, Di,j-1) and the pulse T(Di,j) forms a node Di,j to populate an i×j dimension matrix between the time sequences A and B. the time-domain pulses comparison operation includes operating in a pipeline mode by reading the resultant time pulse T(Di,j) of the (ABS) operation stored in the TFF, for a next cycle MIN operation to form respective nodes Di,j to populate the i×j dimension matrix.
At step 1610, the time-domain hardware implemented method may include a multiplexer (MUX) to facilitate by-pass node pulse data reading from an input TFF to speed up the DTW operations. The stored pulse widths values of the nodes Di,j readings may be improved by performing fine tuning diagonally in the i×j matrix from a bottom right to top left direction. The time-domain hardware may use a NAND gate to perform the ABS operation, wherein only one of the NAND gate's input is buffered by an inverter. The time-domain hardware implemented method also include using a multi-input NOR gate to directly perform the MIN operation on time-domain pulses. The TFF in the pipelines are used to store the resultant time pulse T(Di,j) for a future clock cycle operations and to perform accumulation operations in DTW calculations when enabled. The accumulation function in the TFF may be disabled when not used. In another example, the pipelined structure is scalable by simply cascading the pipelined structure horizontally and vertically to increase sequence length for reading more time sample signals Ai and Bj simultaneously.
Alternate systems may include any combination of structure and functions described or shown in one or more of
Other systems, methods, features and advantages will be, or will become, apparent to one with skill in the art upon examination of the figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the disclosure, and be protected by the following claims.
The present application is a National Stage Entry of PCT International Patent Application No. PCT/US2019/067285 entitled “System and Method for Pipelined Time-Domain Computing Using Time-Domain Flip-Flops and its Application in Time-Series Analysis,” filed on Dec. 18, 2019, which claims priority to and the benefit of U.S. Provisional Patent Application Ser. No. 62/781,425 entitled “System and Method for Pipelined Time-domain Computing using Time-Domain Flip-flops and its Application in Time-Series Analysis,” filed on Dec. 18, 2018, the disclosures of which are all hereby incorporated by reference in their entireties for all purposes.
This invention was made with government support under grant number CCF-1846424 awarded by the National Science Foundation. The United States government has certain rights in the inventions.
Filing Document | Filing Date | Country | Kind |
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PCT/US2019/067285 | 12/18/2019 | WO |
Publishing Document | Publishing Date | Country | Kind |
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WO2020/132142 | 6/25/2020 | WO | A |
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20220019434 A1 | Jan 2022 | US |
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62781425 | Dec 2018 | US |